2023-09-07 12:18 PM
Hello,
I am using a STM32H753. I would like to test the ECC on the L1 cache. In my understanding, a double bit error on the data cache would trigger a BusFault: is there a way to produce it?
Thank you
2023-09-08 06:38 AM
Hello @lwen ,
This might help you to have an idea!
https://github.com/zephyrproject-rtos/zephyr/issues/33140
Thanks,
Ayoub