STM32H74x/75x SDRAM (re-)mapping and caching

[regjoe]

Hello,

maybe this MCU is pretty old but... I'm designing HW for the H75x using SDRAM on bank 1 (SDCKE0+SDNE0).

RM0433 table 154 shows text "SDRAM bank 1" at 0x7000.0000 and 0xC000.0000, also figure 98 but table 7 "Reserved or remap of SDRAM Bank 2".

Q1: Is this an error in the documentation? If so, which table is correct?

Q2: Does this mean that SDRAM is accessible at two different memory regions at the same time, e.g. SDRAM bank 1 at 0x7000.0000 and 0xC000.0000? How, what for?

Q3: I guess that storage in the "External Devices" region (BTW: what does this name stand for?) is not write cacheable, not executeable but read cacheable?

Q4: If the NOR/SRAM bank is remapped to this region, the MCU cannot execute code from this device?

Q5: If the SDRAM is in the "External Memories" region, does this have a significant performance boost e.g. if data is stored here? Is there any drawback?

I have a STM32H753_EVAL2 on my side so I can do some tests if required/recommended.

Best regards

[regjoe]

Hello @SofLit 

sorry for getting back that late.

I spent some time on further investigations but I still can't see any difference if code is executed from 0x7000.0000 or 0xd000.000 in SDRAM Bank2.

For testing, I configured the MPU region for SDRAM like this:

#ifdef DATA_IN_ExtSDRAM
  /* Configure the MPU attributes for SDRAM */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
#ifdef SDRAM_ADDRESS_SWAPPED
  MPU_InitStruct.BaseAddress = 0x70000000;
#else // SDRAM_ADDRESS_SWAPPED
  MPU_InitStruct.BaseAddress = 0xD0000000;
#endif // SDRAM_ADDRESS_SWAPPED
  MPU_InitStruct.Size = MPU_REGION_SIZE_16MB;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
#endif // DATA_IN_ExtSDRAM && SDRAM_ADDRESS_SWAPPED

  HAL_MPU_ConfigRegion(&MPU_InitStruct);

  /* Enable the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

 I undefined SDRAM_ADDRESS_SWAP and placed SDRAM in linker script to 0xd000.0000.

d0000714 <arm_cfft_f32>:
d0000714:	2a01      	cmp	r2, #1
d0000716:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
:

EDIT:

Setting the SDRAM region to MPU_ACCESS_NON_CACHEABLE has the same effect on execution speed as undefining ICACHE_ENABLE.

I seems to me that 0x7000.0000 and 0xd000.0000 can both be configured to cacheable.