tl;dr: accessing external memory over debugger results in additional unwanted write accesses to adjacent memory locations
I have an FPGA that is accessed via FMC over a 16-bit async connection (16-bit data +15-bit address), sort of like an external SRAM. The FPGA contains a PWM module with 16-bit control registers, that are memory mapped to the STM32H745 (e.g. CTRL @ 0x60000000, TIMER_PERIOD @ 0x60000002 and so on). MPU is set to strongly ordered. I set up a svd-file and generated defines, so I can access them like normal periphery, e.g.:
FPGA->TIMER_PERIOD = 0x00FF;
This should write 0x00FF to address 0x60000002. And that works fine in code (at least with async access, synchronous does not).
But, for debugging purposes I want to access these address with the debugger over SWD (J-Link or ST-Link, doesn't matter). Reading works fine. One 16-bit access to the external memory/FPGA is generated. Writing on the other hand produces four 16-bit accesses.
So writing 0x00FF to 0x60000002 via SWD results in:
one write access to 0x60000002 with correct data, but also write accesses to 0x60000000, 0x60000004 and 0x60000006 with unwanted data.
What may be the cause here?
