I'm trying to use the RAMECC monitoring subsystem on an STM32H743 but there's some behaviour I don't understand. I've read the reference manual (RM0433 rev 7) and application note AN5432, as well as some related forum posts here.
If I set an interrupt enable bit in one of the RAMECC_MxCR registers then I get interrupts even if none of the interrupts are enabled in RAMECC_IER.
So it seems like the interrupt enables in RAMECC_MxCR are independent of the per-monitor interrupt enables in RAMECC_IER.
Is this the intended behaviour? It's unclear to me from the reference manual and AN5432.
