STM32H743 Failure behavior with external core SMPS

[SCoen]

Greetings,

right know we are evaluating some strategies to reduces overall power consumption of our product, including two STM32H743 microcontrollers.

Due some other design restrictions the following options are not feasible:

• Switch to a low power µC
• Use the internal low power functions to reduce overall consumption

Basically it boils down to reduce the core voltage: Right know we simply provide 3,3V and the internal regulator feeds the core. With a Clock frequency of 400 MHz it runs at 1,2V resulting in 63% wasted energy from the regulator.

The reference manual mentions the possibility to feed the Core-Voltage from an external source with better efficiency ratio and we'd like to try this.

The design is part of a safety critical system and it is of paramount importance to have a defined output stage on one of our interfaces in case one mcu is defect.

Questions:

• Can you verify that when providing external core voltage of 1,2V the output voltages on all interfaces (GPIO, UART, SPI) are still the same 3,3V, stated that the controllers VDD pins are connected to the 3,3V rail?
• Can you explain what happens to the controller when the externally provided core power supply rises from 1,2V to a maximum of 3,3V? Is there some internal overvoltage protection that cuts the core and puts the µC in reset-state? Are the GPIO-output pins still in a defined state?

Greetings from Germany

Simon

[waclawek.jan]

This is a primarily user-driven forum, and I'm not ST, so for definitive answers you have to contact ST directly.

> Can you verify that when providing external core voltage of 1,2V the output voltages on all interfaces (GPIO, UART, SPI) are still the same 3,3V

GPIO are supplied by VDD/VDDA/VDDUSB, see Pin/ball definition table in DS.

Switching off the internal VCORE voltage regulator does not change the supply scheme, it just does this, switches off the internal VCORE regulator.

> Can you explain what happens to the controller when the externally provided core power supply rises from 1,2V to a maximum of 3,3V?

It will be irreversibly damaged.

While there is no absolute maximum specified for VCORE in DS, I'd consider 1.40V as the highest value in table General operating conditions in DS (plus some reasonable margin, say 5%) to be its absolute maximum.

> Is there some internal overvoltage protection that cuts the core and puts the µC in reset-state?

No.

> Are the GPIO-output pins still in a defined state?

No.

What would you expect happens with GPIO when VDD goes over its absolute maximum (i.e. over 4V)?

JW

[SCoen]

Hi and thanks for the reply.

At the moment the 3,3V rail will be protected against overvoltage above 3,9V. For me, a damaged microcontroller is no problem as long as the GPIO outputs are a defined state. But as you say, this cannot be guaranteed when the core voltage exceeds around 1,4V I have to design some protection for a malfunctioning 1,2V stepDown converter.

I will contact ST directly and post their reply here.

Simon