STM32H7 why is Dcache faster than DTCMRAM ?

[xchen.3]

I am benchmarking Stm32h7 processor on floating point operations and using CYCCNT to measure the performance difference .

I placed my function in ITCM-RAM. which is just a function that does double math multiplication 10,000 times, the 4 variables used are declared volatile.

I placed my variables in RAM ( with D-cache disable) : CYCCNT = 216849

I placed my variables in RAM ( with D-cache enable) : CYCCNT = 104300

I placed my variables in DTCM-RAM ( with D-cache disabled/enabled same result) : CYCCNT = 115800

my question is why is DTCM slower than RAM1 with cache ??!!

[xchen.3]

that is something new . thank u for pointing it out . can you please provide reference for this ? I haven't read anywhere about benefit of cashe vs TCM . regards

[waclawek.jan]

Try reloading the thread, until you see "More answers" under the 10th post.

JW

[Piranha]

Guys, you're talking with a bot... 😉

https://stackoverflow.com/questions/59198934/l1-cache-behaviour-of-stm32h7

https://community.st.com/s/question/0D50X0000BmnJAWSQ2/setup-licache-on-stm32h753

On topic... Just a guess, but, looking at the core architecture images, it could be that ITCM and DTCM share some resources or arbitration logic:

http://www.emcu.it/STM32F7/Slide/Core.png