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STM32H7: what is the proper way to make SPI work in master mode?

JoMercury
Associate

Am working on a SPI driver for STM32H7 (for Ada language).

I use the board Nucleo-H743ZI.

I'd like to make SPI4 working as a master in full dulplex mode (no DMA mode).

What are the proper steps to follow? the reference manual is not very specific (for me as beginner)

I tried to follow the C code, but I think am missing something.

For the moment what I did:

- I configured the GPIO pins SCK to PE2 / MISO to PE5 / MOSI to PE6

- The clocks of the GPIO pins are set to Alternate Function mode (value 5), resistors to Pull_Down, speed to 100Mhz, the output type to Push_Pull.

- I enabled the clock for the port SPI4

-- APB2ENR.SPI4EN register set to 1

- I made sure the SPI is disabled to start configuring it

-- SPI4.CR1.SPE is false

[When I set the the SPI4.CFG2.MASTER to 1 (mode Master), the Mode Fault flag (SPI4.SR.MODF = 1) is raised and can't enable the SPI port anymore.

When then I try to set the flag to 0 using the register IFCR.MODFC to 1, the SPI4.CFG2.MASTER returns to 0.

Infinite loop...] solved thanks to @Community member​ 

[Update 1]

By default the SPI is in slave mode, I need to fix the SS for master.

It woks using :

CR1.SSI := 1

CFG2.SSM  := 1

And keep CFG2.SSOE to 0

Then I set CFG2.MASTER to 1 and CR1.SPE to 1 to enable the SPI in master mode.

For transmitting I set CR2.TSIZE to >0 value.

Else you will never get the SR.EOT.

To transmit data (8bits mode CFG1.DSIZE := 7) I write TXDR := 5 (for test).

Then I set CR1.CSTART to 1.

In the debug I get the SR.EOT.

Am trying to get the signal from the SCK to PE2 / MISO to PE5 / MOSI to PE6 in the scope.

1 ACCEPTED SOLUTION

Accepted Solutions

Read the fine manual.

Master mode fault (MODF)

Mode fault occurs when the master device has its internal SS signal (SS pin in SS hardware

mode, or SSI bit in SS software mode) pulled low. [...]

If you don't intend to use the NSS pin (N there stands for Negated), set both SPI_CFG2.SSM and SPI_CR1.SSI.

JW

View solution in original post

1 REPLY 1

Read the fine manual.

Master mode fault (MODF)

Mode fault occurs when the master device has its internal SS signal (SS pin in SS hardware

mode, or SSI bit in SS software mode) pulled low. [...]

If you don't intend to use the NSS pin (N there stands for Negated), set both SPI_CFG2.SSM and SPI_CR1.SSI.

JW