STM32H7 SPI flash fast read timing calculation

[regjoe]

Hello,

I have a NOR SPI flash connected to single SPI interface of a H75x MCU and want to use the highest possible SPI frequency for data read. The core clock is 400MHz, so I can chose between 50 and 100MHz.

According to the data sheets the "Clock low to output valid" time tv of the IS25WPxxx is 7-8ns, the H7 setup time is 1-2ns. This means the half period (SPI clock low time between falling and rising edge) must be at least 10ns. Assuming high and low pulse are the same, this means the max. clock is 50MHz in this simple calculation, which is not considering signal transmission delays, signal rise/fall times and switching voltages.

I found out that most flash have implemented a "NORMAL READ" and a "FAST READ". Both differ in the max. SPI clock, for example 80MHz for READ and 166MHz for FAST READ transfer. Unfortunately, looking at the timings, I do not understand why the FAST READ frequency is twice the READ transfer frequency.

The meaning of tv is explained here:

This means that data on SO is valid after tv after the falling clock edge has been detected. Here only 1 read is shown here but I guess that all subsequent data reads are affected by the same tv.

Looking at the following timing of the FAST READ, it seems that tv does only come into play once, after the dummy bytes sent and the first data bit read.

Usually, in mode 0, data is shifted at falling edge and sampled at rising edge. Here it looks that this is only the case for the first data bit. For all subsequent bits the timing suggests that data is shifted at rising and sampled at falling edge.

How does this work? How can this timing explain the higher FAST READ frequency?

I would have expected that the first bit is valid after tv=7/8ns but the subsequent bits are valid somewhat faster, eg. after 2ns or something like that, or how can this device output data at 166MHz if tv is 7-8ns?
Any idea?

[TDK · Accepted solution]

tv is a delay on all bits coming from SO, not just the first. All data out bits are delayed by 7-8 ns. If your clock is slow enough, this doesn't matter. Otherwise you have to add a dummy cycle or add a delay somewhere to get it to sync up with your clock. I don't think the basic SPI peripheral can do this, but maybe the NOR flash specific one can.

[regjoe]

Hi @TDK ,

the STM32H7 SPI can insert extra clock cycles after each data frame using the MIDI parameter:

Inserting a dummy cycle after each single bit would delay the MCU sample point, just what I needed to run this device at 50Mbit/s with SPI Clock at 100MHz. But unfortunately the data frame size can be only be configured to 4...32 bit.

Bits 4:0 DSIZE[4:0]: number of bits in at single SPI data frame
00000: not used
00001: not used
00010: not used
00011: 4-bits
00100: 5-bits
00101: 6-bits
00110: 7-bits
00111: 8-bits
.....

I checked out the "unused" DSIZE value 0 but the dummy clock cycle is inserted after the 4th bit.

Is there another way to shift/delay the H7 sample point, which is at the rising edge in mode 0?