STM32H7 FMC Interface to External Memory. Running code from external memory.

[KGane.1]

Hi,

I am considering upgrade from STM32F4 series to STM32F7 or STM32H7(single core) series. However, the H7 embedded memory is not enough for the requirement. I would like to run simple RTOS scheduler. So there is need for external memory.

-QuadSPI interface - Flash(code and config storage)

I would like to interface the following through FMC

-PSRAM(program memory)

-SRAM(data memory)

-FPGA(memory mapped)

I have two questions.

1. What are the drawbacks of running code from external memory
2. Is it possible to interface(PSRAM,SRAM and FPGA to FMC)

Thanks

[TDK]

> What are the drawbacks of running code from external memory

It will be slower, and it's more complicated to load code onto external memory than the internal flash.

> Is it possible to interface(PSRAM,SRAM and FPGA to FMC)

PSRAM/SRAM yes. An FPGA can appear as anything, so yes, assuming you have compatible code on it. I would recommend doing a pinout in CubeMX to verify all pins are available.

[Tesla DeLorean]

Some reason you'd use SRAM/PSRAM over a large SDRAM?

You can have up to 256 MB of QuadSPI Flash allowing for execute-in-place. Can be banked to provide 8-bit.

eMMC on the SDMMC could provide for very large storage of data/code.

Watch out for having enough select pins, although you could divide down and decode a larger one externally.

[KGane.1]

@TDK​ Thanks. Agree. There would be lot of work in bootloader to load code from external flash to external RAM.

Reference manual says..."The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared."

So using chip select, we can map

-PSRAM to FMC-NOR Flash/PSRAM Controller NE[1]

-SRAM to FMC-NOR Flash/PSRAM Controller NE[2]

-FPGA to FMC-NOR Flash/PSRAM Controller NE[3]

or

-PSRAM to FMC-NOR Flash/PSRAM Controller NE[1]

-SRAM to FMC-NOR Flash/PSRAM Controller NE[2]

-FPGA to FMC SDRAM Controller

@Community member​ Thanks. Seems i have to read application note about QuadSPI Flash XIP. Would it affect performance comparing to parallel interface?

[Tesla DeLorean]

Caching should mask the inherent/relative slowness of the SDRAM, or QSPI external memories.

Code could always be copied into a RAM.

In indirect mode the QSPI can address 4GB devices.