Hello @Gpeti,
Firstly, I would like to clarify this erratum. So, the issue is rather cosmetic and has no impact concerning correct data handling. In fact, the end part of the last SCK cycle (not used for any data bit handling) flow can be distorted once the last bit is sampled.
At dependency on CPHA setting, the user can observe an asymmetrical and shorter the last SCK period with a premature end as the data sampling process is terminated internally. And EOT event is raised still within this possible affected cycle duration.
As the signal deformation appears after SW control exclusively, then it depends how fast is the SW reaction on the EOT event and what is the ratio between pclk and SPI baud rate, mainly if SPI disable action is propagated still within the rest of the last SCK period. At this case, only the not expected signal deformation can be observed.
Anyway, the data should never be corrupted by that as this can happen once the data is fully sampled and/or propagated in/out. Note if baud rate is pclk/2 you have no chance to observe that issue as, e.g., context saving at entry to EOT interrupt service takes a few pclk cycles consumed prior to any SW starts its execution inside the handler. So, such an EOT SW handling usually appears significantly later with a delay of a few SCK periods (far from the end of the last critical one).
Thank you for your contribution in the community.
Kaouthar
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