Showing results for 
Search instead for 
Did you mean: 

STM32H7 ADC characteristics



I'm working on a setup with a filter and some electronics to get an analog signal ready for a ST microcontroller (STM32H723VG). I want to simulate everything, even the part inside the microcontroller that handles the signal. But the problem is, I can't find the info I need in the microcontroller's manual. The manual does have a table that shows how long it takes to sample different signals, depending on how much resistance the source has. But I'm not sure how to use this info to figure out the resistance and capacitance inside the microcontroller.
So far, I've tried to guess the resistance and capacitance by looking at the sampling times in the table. I came up with a guess of 1K ohm for the resistance and 8.5 pF for the capacitance. But I'm not sure if 1 kilo-ohm is right. I want to sample at about 4MSPS, but 1 kilo-ohm might be too much resistance to do that quickly enough within 0.5LSB and with the required sampling time of 60-70 nanoseconds.

Here are some details about the setup:

Microcontroller: STM32H723VG
ADC input range: 0-3.3V
Signal Bandwidth: 1MHz (-3db)
Filter attenuation at 4MHz: -40db
ADC Resolution: 12 bits
ADC channel type: Fast Channel
ADC Clock: 40MHz
Sampling time (2.5): 62ns
Sampling frequency in dual mode: 8MSPS (two ADC at 4MSPS)

Note: The images show the last stage for level shifting, charge bucket and ADC internal

Any help or advice would be great.


STM32H723VG datasheet.pngSTM32H7.png

ST Employee

Hello @HKet 

The table in Datasheet gives the minimum sampling time for external RAIN of analog source.

It does not give the internal model of ADC peripheral.

But, if you need to design the external OPAMP circuit to reach 4MSPS per ADC on Fast channel, we can provide sampling time plot  (ADC sampling time function of RAIN and CAIN/CPCB like below:


Here the ADC sampling time plot for Fast channel with 12bit resolution , and the table that shows all parameter around 4MSPS

RAIN = 68 Ohms and CAIN = 47 pF


Let me know if it can help?

Best regards,







To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.


Hey Romain,

Thanks for getting back to me.

Could you please explain what exactly the "1lsb error" in the table refers to? Does it indicate that the voltage on the sample and hold capacitor after the acquisition time (before the conversion) will be less than 0.5 LSB from the input or less than 1 LSB?

Will we achieve the same result in dual ADC mode with these input resistance and capacitance values?