2025-07-01 12:30 PM - last edited on 2025-07-01 11:50 PM by Imen.D
Greetings,
I am using STM32CubeIDE version 1.18, Running FreeRTOS, and using the HAL
library to configure the ETH device.
I have the STM32H573 ETH port configured as MII, and communicating with an external
ethernet switch device (also in MII mode). We want the link to be Full Duplex 10 Mbps.
We can see that the MAC CR register has bit 14 as a zero, which is 10 Mbps mode.
GRISHKA $ peek 0x40028000
[40028000] 0x3830A003
Yet, we I probe the RX and TX clocks with my scope, I see both clocks at 25 Mhz (40 nsec period).
I believe at 10 Mbps, the clock frequency should be 2.5 Mhz (400 nsec period) ?
Thanks
Ken Carlson
Edit by ST Moderator: Add the right labels
2025-07-16 8:24 AM
Hello @microcoder ,
Thank you for your patience. After researching the issue and testing your configuration, I found that the PLL clock output must be between 128 MHz and 560 MHz, as specified in DS14121. In your setup, the 25 MHz HSE divided by 2 (PLLM) gives 12.5 MHz, multiplied by 10 (N) equals 125 MHz, and divided by 2 (PLLQ) results in 62.5 MHz.
This 125 MHz PLL clock does not meet the minimum required frequency.
To resolve this, please try increasing the multiplier (N) to at least 11 to meet the minimum clock requirement. Let me know how it goes.
Best regards,
2025-07-17 2:17 PM