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STM32H562 FLASH Prefetch and ICACHE

Markus8494
Associate II

Hello,

I am currently evaluating the STM32H562 device. This devices has an ICACHE (instruction cache) module.
Does it make sense to enable both, the ICACHE module and the FLASH prefetch buffer?

 

In the past I already worked with the G0, G4 and F4 series.
If I create an STM32G474 CubeIDE project, I can enable the FLASH "Instruction cache" and the "Prefetch buffer" via the "RCC" module.
If I create an STM32H562 CubeIDE project, I can enable the "ICACHE" module but there is no "Prefetch buffer" setting in the "RCC" module anymore.

Is there a reason that the "prefetch buffer" enable option is not available for the H562 device in the CubeIDE?

What is the difference between the "FLASH Instruction cache" of the G4 and the "ICACHE" module of the H5?

Thank you,
Markus

1 ACCEPTED SOLUTION

Accepted Solutions
STOne-32
ST Employee

Hi @Markus8494 ,

 

You can refer to this architecture and system diagram to have more details on differences with Cortex-M33 core vs M4 on STM32 MCUs series . The question is excellent ! 

IMG_6194.jpeg

IMG_6193.jpeg


Hope it helps you .

Cheers,

STOne-32 

View solution in original post

4 REPLIES 4
SofLit
ST Employee

Hello,

Simply the "FLASH Instruction cache" or Prefetch buffer is dedicated to the Flash but Cache implies also to other memories either internal or external so it adds access performance to other memories.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
STOne-32
ST Employee

Hi @Markus8494 ,

 

You can refer to this architecture and system diagram to have more details on differences with Cortex-M33 core vs M4 on STM32 MCUs series . The question is excellent ! 

IMG_6194.jpeg

IMG_6193.jpeg


Hope it helps you .

Cheers,

STOne-32 

Piranha
Chief II

The FLASH I-cache on G4 is 1 KB, while the CPU I-cache on H5 is 8 KB and works also for SRAM and external memories. The FLASH prefetch is clearly explained in the RM0481 section 7.3.4. It's impact on performance is not so significant as from the I-cache, but it still improves the performance slightly and it makes sense to enable both. The fact that it's not present in CubeMX - well, it's your choice whether to believe the marketing nonsense about code generation and be dependent on some broken bloatware or to do an actual software development...

Markus8494
Associate II

Thank you all for your quick responses.

@PiranhaI also usually prefer the more direct methods like the LL- or HAL library functions and/or direct register access. But I have to admit, that the CubeIDE has some features, that saved me some time in the past (for example, quickly getting the PLL factors for different clock/clock source configurations)