STM32G4: ADC sampling and hold capacitor value

[tssh]

Setup

• STM32G491KE
• ADC1 Input Channel 3 using Pin PA2
• Vdd = 3V
• RC-Filter at the ADC input with R = 33 Ohm, C = 330 pF

Observation

When measuring the voltage at the ADC input with an oscilloscope, we see the voltage drop caused by switching the input signal to the SAR-ADC capacitor (C_ADC). This voltage drop and its settling depends on the used RC-Filter (values see above).

We also observe that if the ADC input voltage is around Vdd/2, the voltage drop suddenly jumps by factor 2. Namely, if we compare the voltage drop at input voltage 1.45V with the voltage drop at input voltage 1.52V, the voltage drop is doubled for the input voltage 1.52V (see the plot in the attachment).

However, if the capacitor of the ADC (C_ADC) is constant and the capacitor is completely discharged during the conversion phase of the ADC, we would expect only a linear dependency of the voltage drop to the input voltage of the ADC.

Question(s)

• Is there an explanation for this voltage jump at Vdd/2 (and possibly other other voltage levels)?
• Can this behavior be explained by the architecture of the ADC input buffer?
• Are there possible measures or any recommendations to mitigate this behavior?

[Michal Dudka]

Sampling capacitor (Cs) is about 5pF. If Cs is fully discharged when sampling starts it should make a step about 5pF/330pF*1.45V = 22mV and that corresponds with your reading.

Are you sure that Cs must be fully discharged during conversion phase ?

[tssh]

> Are you sure that Cs must be fully discharged during conversion phase ?

That is an assumption from my side, but I didn't find any information about that. If ST could confirm that the SAR-ADC capacitor C_ADC is not necessarily fully discharged during the conversion phase, this would explain our observations.

[Michal Dudka]

I think that C_ADC is not discharged during conversion. With STM32F0 i've been able to observe "memory cross talk" which is caused by capacitor charge from previous measurment/channel.

[Igor Cesko · Accepted solution]

Dear tssh ,

The behavior at Vref/2 input voltage is expected. The design of ADC is like changing residual voltage on sampling capacitor. If more channels are scanned by ADC the residual voltage is influenced from the previous channel voltage. Therefore the prediction of residual voltage on the capacitor is not predictable (due to previous channel voltage dependency) - and it is difficult to linearize the system.

The input RC filter (33Ohm, 330pF) must be designed that the final voltage at the end of sampling time (charge from 330pF will be distributed to 330pF+5pF and charged a bit through 33Ohm resistor) must be almost the same as on 330pF before sampling (~1LSB difference). Otherwise there will be voltage decrease on 330pF capacitor. Better is to not use the capacitor in front of ADC input (together with resistor) - because the time constant of this RC filter is usually much longer that ADC sampling time => we measure a bit less voltage. We have application note where is this a bit described: AN2834 (chapter 4.4 High impedance source measurement) .

Better is to not use small capacitor on ADC input. Or we should use very large capacitor and sample in very low frequency (see AN2834).

Regards

Igor