STM32G030 erratum 2.2.1 workaround is not reliable

[DAlbe.3]

Erratum 2.2.1 (Unstable LSI when it clocks RTC or CSS on LSE) indicates the following workaround:

If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each VDD power up
(when the BORRSTF flag is set). If VBAT is separate from VDD, also restore the RTC configuration, backup
registers and anti-tampering configuration.

Although this works much of the time, sometimes it does not. This seems to be related to exactly what happens on the Vdd rail: if Vdd gets low enough to set the RCC_CSR PORRSTF but not below ~0v6, then the LSI sometimes runs fast (~48.9kHz) on startup, even if the workaround (reset backup power domain) is implemented.

Unfortunately, in the real world, this Vdd scenario happens: when main power glitches, bulk capacitance in most designs will gradually drain and will drain especially slowly once Vdd falls below MOSFET switching thresholds. When power comes back, Vdd may not have gotten all the way to 0V and this issue can manifest despite the workaround.

For reference, the workaround is implemented as follows:

    SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); // enable clock to pwr control subsystem
    // Start LSI oscillator used by RTC and IWDG
    SET_BIT(PWR->CR1, PWR_CR1_DBP);           // enable access to backup power domain
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET);
    // See Errata 2.2.1: Unstable LSI after main power domain reset
    // if reset was due to POR or BOR, reset the backup power domain
    if (RCC->CSR & RCC_CSR_PWRRSTF) {
        SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);       // reset backup power domain
        while(READ_BIT(RCC->BDCR, RCC_BDCR_BDRST) == RESET);
        CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
    }
    // Start LSI and wait until ready
    SET_BIT(RCC->CSR, RCC_CSR_LSION);         // turn on LSI oscillator
    while (!(RCC->CSR & RCC_CSR_LSIRDY));     // wait for LSI ready
    CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);

Most of the time, the LSI will start and run at 32kHz, but periodically, it will still run at 48.9kHz and then only a POR will clear the condition.

For designs without an LSE, this is a critical condition.  The ugly workaround is to measure the LSI with the HSI and then choose prescalers based on the actual frequency.

[Bubbles]

Hi @DAlbe.3 ,

thanks for sharing the additional details. I realize that with voltage dropping this low, BOR setting is probably irrelevant.

If the fail mechanism is the same as the one the workaround is trying to correct, then the cause is the system is correctly reset (all that is normally supplied by the VDD) while the backup domain (VBAT powered) keeps requesting the LSI.

It's a wild guess from my side, but perhaps if more load was present on the backup domain, the voltage normally associated with VBAT (internally it's still present on the die) would drop faster and cause reset also to the backup domain. Maybe if more RTC and TAMPER features are configured, it will improve.

Regarding the caps, I know this is exactly what we recommend, but what if these quality caps actually keep the backup domain up?

BR,

J