STM32F756BGT6 GPIO State Under/During Reset - High-Z or Input with Pull-up or something else?

[JLi.10]

Hi everyone,

I have a question regarding the STM32F7 family, more specifically the STM32F756BGT6: what is the GPIO state when it's held under reset, i.e. the NRST pin is held LOW? Are the GPIOs in high impedance state or input with pull-up or something else? Also I'd like to learn where this information is located in the datasheet of STM32F756BGT6 as I couldn't find it.

Thank you very much!

Jianan

[waclawek.jan]

See reference manual (RM) GPIO chapter, description of MODER and PUPDR registers.

JW

[TDK]

Most pins are high-z input without pullup/down except those used by SWD/JTAG.