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STM32F7 SPI DMA triggered by EXTI

mchomnicki9
Associate II
Posted on October 20, 2017 at 14:50

Hi All

I'm looking for solution. I have to communicate my external ADC with STM32F7 by SPI. I have request from ADC on DRDY pin with 50kHz, which I set as EXTI in the procesor. But how to control SPI DMA by this DRDY PIN? On each falling edge on DRDY, SPI should read 12Bytes. 

I want to fill buffer with e.g. 500 data rates from ADC and then do something with it.

My code:

/* SPI1 controller clock enable */

__SPI1_CLK_ENABLE();

/* DMA controller clock enable */

__HAL_RCC_DMA2_CLK_ENABLE();

/* DMA interrupt init */

/* DMA2_Stream0_IRQn interrupt configuration */

HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, DMA2_Stream0_IRQn_Priority, DMA2_Stream0_IRQn_SubPriority);

HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);

/* DMA2_Stream3_IRQn interrupt configuration */

HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, DMA2_Stream3_IRQn_Priority, DMA2_Stream3_IRQn_SubPriority);

HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);

/* Peripheral DMA init*/

dma_rx_handle.Instance = DMA2_Stream0;

dma_rx_handle.Init.Channel = DMA_CHANNEL_3;

dma_rx_handle.Init.Direction = DMA_PERIPH_TO_MEMORY;

dma_rx_handle.Init.PeriphInc = DMA_PINC_DISABLE;

dma_rx_handle.Init.MemInc = DMA_MINC_ENABLE;

dma_rx_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;

dma_rx_handle.Init.MemDataAlignment = DMA_PDATAALIGN_BYTE;

dma_rx_handle.Init.Priority = DMA_PRIORITY_MEDIUM;

dma_rx_handle.Init.Mode = DMA_CIRCULAR;

dma_rx_handle.Init.FIFOMode = DMA_FIFOMODE_ENABLE;

dma_rx_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;

dma_rx_handle.Init.MemBurst = DMA_MBURST_SINGLE;

/* Deinitialize the stream for new transfer */

HAL_DMA_DeInit(&dma_rx_handle);

if (HAL_DMA_Init(&dma_rx_handle) != HAL_OK)

{

while(1);

}

__HAL_LINKDMA(&hspi1,hdmarx,dma_rx_handle);

/* SPI1_TX Init */

dma_tx_handle.Instance = DMA2_Stream3;

dma_tx_handle.Init.Channel = DMA_CHANNEL_3;

dma_tx_handle.Init.Direction = DMA_MEMORY_TO_PERIPH;

dma_tx_handle.Init.PeriphInc = DMA_PINC_DISABLE;

dma_tx_handle.Init.MemInc = DMA_MINC_DISABLE;

dma_tx_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;

dma_tx_handle.Init.MemDataAlignment = DMA_PDATAALIGN_BYTE;

dma_tx_handle.Init.Priority = DMA_PRIORITY_MEDIUM;

dma_tx_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

dma_tx_handle.Init.Mode = DMA_CIRCULAR;

/* Deinitialize the stream for new transfer */

HAL_DMA_DeInit(&dma_tx_handle);

if (HAL_DMA_Init(&dma_tx_handle) != HAL_OK)

{

while(1);

}

__HAL_LINKDMA(&hspi1,hdmatx,dma_tx_handle);

// HAL_NVIC_SetPriority(SPI1_IRQn, SPI1_IRQn_Priority, SPI1_IRQn_SubPriority);

// HAL_NVIC_EnableIRQ(SPI1_IRQn);

// SPI configuration

hspi1.Instance = SPI_NUMBER;

hspi1.Init.Mode = SPI_MODE_MASTER;

hspi1.Init.Direction = SPI_DIRECTION_1LINE;

hspi1.Init.DataSize = SPI_DATASIZE_8BIT;

hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;

hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;

hspi1.Init.NSS = SPI_NSS_SOFT;

hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;

hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;

hspi1.Init.TIMode = SPI_TIMODE_DISABLED;

hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;

hspi1.Init.CRCPolynomial = 7;

hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;

hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;

HAL_SPI_Init(&hspi1);

inkr_buff_spi = 0;

HAL_SPI_Receive_DMA(&hspi1, (uint8_t *) &SPI_RX_BUFF[inkr_buff_spi], sizeof(SPI_RX_BUFF) );

//HAL_SPI_TransmitReceive_DMA(&hspi1, SPI_TX_BUFF, (uint8_t *) &SPI_RX_BUFF[inkr_buff_spi], sizeof(SPI_RX_BUFF) );

HAL_NVIC_SetPriority(SPI_ADS1274_RDY_EXTI_IRQn, SPI_ADS1274_EXTI_Priority, SPI_ADS1274_EXTI_SubPriority);

HAL_NVIC_EnableIRQ(SPI_ADS1274_RDY_EXTI_IRQn);

#stm32f7
3 REPLIES 3
Alan Chambers
Associate II
Posted on October 20, 2017 at 16:30

Why not just start the DMA transfer from the EXTI ISR? 

mchomnicki9
Associate II
Posted on October 20, 2017 at 16:41

Hi,

Because transmitting in DMA_NORMAL mode on each EXTI ISR take to much resources. You can see on the time diagram.

0690X000006044dQAA.jpg

Posted on October 20, 2017 at 16:58

Ah. I missed the 50kHz part. Not sure why the ISR should take ages, though.