STM32F7: SPI and DMA FIFO advices

[ZNifi.1]

Hello!

I’m pretty new at STM32 and I have small hobby project with STM32F7 series.

I used LL library.

I communicate with external sensors through SPI. STM32 – master, external sensors – slaves. External sensors “data ready�? pins allow me to initiate data transfer requests. Data packets pretty small and frequent: 7 bytes, 11 bytes (different sensors) and ~4kHz frequency.

I used DMA for sending\receiving this data. It configured like this:

        LL_DMA_InitTypeDef init = {};
        …
        init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
        init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
        init.Mode = LL_DMA_MODE_NORMAL;
        init.FIFOMode = LL_DMA_FIFOMODE_ENABLE;
        init.FIFOThreshold = LL_DMA_FIFOTHRESHOLD_FULL;
        init.MemBurst = LL_DMA_MBURST_SINGLE;
        init.PeriphBurst = LL_DMA_PBURST_SINGLE;
        …

I restarted DMA send\receive transfer after every “data ready�? external sensors signal with fixed data length (7 and 11 bytes).

I have some questions:

1. Is it a good\bad idea to set DMA FIFO to enabled in this case (fixed send\receive transfer length)? Or should I just disable it?
2. If I will set receive DMA stream (with enabled FIFO) to circular mode: does it mean that I will receive actual data only after whole FIFO filing (or part 4/8/12/16 bytes but not 7 or 11)?
3. Should I change MemoryOrM2MDstDataSize\MemBurst\PeriphBurst settings in my case? I can increase transfer size if it’s necessary.

Note: I use onboard cache (enabled ICache and DCache and prepared memory regions for DMA buffers with right attributes by tuning MPU). Not sure does it affects answers on my questions.

[TDK · Accepted solution]

> Is it a good\bad idea to set DMA FIFO to enabled in this case (fixed send\receive transfer length)? Or should I just disable it?

I'd generally go with direct mode. FIFO can help alleviate bus issues which is useful if you're heavily using the bus for other stuff. Doesn't seem like that's the case here.

> If I will set receive DMA stream (with enabled FIFO) to circular mode: does it mean that I will receive actual data only after whole FIFO filing (or part 4/8/12/16 bytes but not 7 or 11)?

Yes, the FIFO is only flushed when the threshold is reached. Another reason to keep direct mode.

> Should I change MemoryOrM2MDstDataSize\MemBurst\PeriphBurst settings in my case? I can increase transfer size if it’s necessary.

Since you're doing 7 and 11 byte transfers, you have to keep the datasize to byte. Burst setting is ignored in direct mode.

> Note: I use onboard cache

Make sure the tx cache is cleaned before sending and the rx cache is invalidated prior to reading. Make sure each are in isolated cache pages. Or manage cache in some other manner.

[ZNifi.1]

Thank you very much for comprehensive answers!

> Make sure the tx cache is cleaned

Yes of course. Aligned buffers, I tried both scenarios: use cache management instructions (like __DSB,SCB->DCCMVAC=send, SCB->DCIMVAC = received,__DSB,__ISB) and preconfigured MPU regions. Last one looks more comfortable in my case.