I have a STM32H7 with it's FMC signals hooked up to an FPGA in order to allow the microcontroller to peak/poke into FPGA registers. I had a FIFO in this address space that, if read, would automatically increment to the next value. I was noticing on occasion having two read requests for what should be only a single read in the code (causing data loss on the FIFO). I found this old post: https://community.st.com/t5/stm32-mcus-products/stm32f7-fmc-dummy-read/td-p/419015 in which someone saw the same issue and found out that interrupts were coming in causing the FMC to repeat the read once returning from the interrupt handler. I tried disabling interrupts and saw my problem go away.
What's odd is that I saw this happening very frequently on reads (occurring anywhere from a couple hundred to a few thousand reads in) but when stressing the writes at the same level, I never saw this occur. The difference in time to finish a read/write doesn't seem to be different enough to explain the disparity. Is there something I'm missing internally that may explain this difference?
