STM32F7/RAM/ST7789H2 issues

[Charles GORAND]

Posted on July 16, 2018 at 10:36

Hi,

We have our custom board with a STM32F746ZG and we have RAM memory and a screen controller (ST7789H2). The screen is connected through parallel port.

If I enable the RAM memory only, there is no issues. If I enable RAM memory and display, I got memory corruptions.

If I enable only the screen, it's working but I'm not able to draw on full screen. I'm able to read manufacturer ID but when I draw on screen, pixels are drops or badly interpreted ('kind of bit shifted'). I tried differents values for 'sram_timing' and was not able to get a valid result. I have tried using values greater than minimal values from screen datasheet, change the MCU frequency(50, 144, 180 MHz ...) no improvement.

We already implemented this on a STM32F426 and it's working perfectly.

Here the configuration :

• RAM memory :

FMC_SDRAM_TimingTypeDef SdramTiming;
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
SdramTiming.ExitSelfRefreshDelay = 7;
SdramTiming.SelfRefreshTime = 4;
SdramTiming.RowCycleDelay = 7;
SdramTiming.WriteRecoveryTime = 2;
SdramTiming.RPDelay = 2;
SdramTiming.RCDDelay = 2;
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
 // handle error
}
else
{
 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
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• FMC init for display :

HAL_StatusTypeDef halStatus;
FMC_NORSRAM_TimingTypeDef sram_timing;
result = DisplayApi::SUCCESS;
/* Enable FSMC clock */
__HAL_RCC_FMC_CLK_ENABLE();

/*** Configure the SRAM Bank 1 ***/
/* Configure IPs */
hsram.Instance = FMC_NORSRAM_DEVICE;
/* Timing for READING */
sram_timing.AddressSetupTime = 0;
sram_timing.AddressHoldTime = 15;
sram_timing.DataSetupTime = 7;
sram_timing.BusTurnAroundDuration = 0; // Not used
sram_timing.CLKDivision = 0; // Not used
sram_timing.DataLatency = 0; // Not used
sram_timing.AccessMode = FMC_ACCESS_MODE_A;
hsram.Init.NSBank = FMC_NORSRAM_BANK1;
hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hsram.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
hsram.Init.PageSize = FMC_PAGE_SIZE_NONE;
hsram.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
/* Initialize the SRAM controller */
halStatus = HAL_SRAM_Init(&hsram, &sram_timing, nullptr);
if (halStatus != HAL_OK)
{
 // Handle error
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Thank you for help.

#stm32f746 #fmc-sdram