2022-03-25 03:17 AM
void init(){
RCC->AHB1ENR = RCC_APB1ENR_TIM12EN | RCC_APB1ENR_TIM13EN | RCC_APB1ENR_TIM14EN | RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN |
RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMA2EN | RCC_AHB1ENR_CRCEN | RCC_AHB1ENR_BKPSRAMEN;
RCC->APB1ENR = RCC_APB1ENR_USART2EN | RCC_APB1ENR_TIM3EN | RCC_APB1ENR_PWREN;
RCC->APB2ENR = RCC_APB2ENR_USART6EN | RCC_APB2ENR_EXTIEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADC3EN | RCC_APB2ENR_TIM1EN;
// init PC6 & PC7 for USART6 (AF8)
Peripherals::Gpio::Pin(GPIOC, 6).setAlternateFunction(8); //USART6_TX
Peripherals::Gpio::Pin(GPIOC, 7).setAlternateFunction(8); //USART6_RX
DMA2_Stream6->PAR = reinterpret_cast<uint32_t>(&USART6->DR); //Peripheral-to-memory
DMA2_Stream6->M0AR = reinterpret_cast<uint32_t>(m_buffer); //Memory-to-peripheral
Cpu::setIrqHandler(usartIrq, &usartIrqHandler);
Cpu::setIrqHandler(dmaIrq, &dmaIrqHandler);
Cpu::enableInterrupt(usartIrq);
Cpu::enableInterrupt(dmaIrq);
//baud rate : CLK/(16 * BRR) = 57600 bps
//-> BRR = CLK / (16 * 57600) = 40MHZ / (16 * 57600) = 43.403
USART6->BRR = 0x2b6; //43.375
USART6->CR3 = USART_CR3_DMAT; //DMA Enable Transmitter
USART6->CR1 = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;//RXNE interrupt enable, Transmitter enable, Receiver enable, USART enable
}
void
dmaIrqHandler()
{
DMA2->HIFCR = DMA_HIFCR_CTCIF6;
DMA2_Stream6->CR = 0;
SET_BIT(USART6->CR1, USART_CR1_TCIE);
}
void
usartIrqHandler()
{
uint8_t status = USART6->SR;
uint8_t data = USART6->DR;
if ((status & (USART_SR_PE | USART_SR_FE | USART_SR_NE | USART_SR_ORE)) == 0) {
s_instance->handleIncomingByte(data);
}
if (status & USART_SR_TC) {
CLEAR_BIT(USART6->CR1, USART_CR1_TCIE);
}
}
void
BypassCommunication::prepareAndSubmitRequest()
{
//m_buffer gets filled here but code is removed
CLEAR_BIT(USART6->SR, USART_SR_TC);
DMA2_Stream6->NDTR = m_length;
DMA2_Stream6->CR = DMA_SxCR_CHSEL_2 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 |
DMA_SxCR_TCIE | DMA_SxCR_EN;
}
When I call prepareAndSubmitRequest() the dmaIrqHandler() is never executed.
What is wrong with my setup?
2022-03-25 06:32 AM
> DMA2_Stream6->CR = DMA_SxCR_CHSEL_2 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 |
DMA_SxCR_TCIE | DMA_SxCR_EN;
JW
2022-03-25 06:38 AM
DMA2_Stream6->CR =
DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_2 | // channel 5
DMA_SxCR_MINC | DMA_SxCR_DIR_0 | // memory-to-peripheral, increment memory addr
DMA_SxCR_TCIE | DMA_SxCR_EN; // enable channel & complete interrupt
Got it now thx