STM32F427VIT I2S strange desync problem

[miavenitoidee123]

Posted on July 10, 2014 at 11:11The original post was too long to process during our migration. Please click on the attachment to read the original post.

[schauer]

Posted on July 11, 2014 at 15:56

Ok, I do have the same situation here with SRC4392 and STM32F427. From what I have understood the situation is as follows:

1) there is a SRC4392 with an 24,576 MHz external oscillator or something like that (maybe half that frequency?) 2) a STM32F427 with an 8MHz HSE running at a multiple of 42MHz (possible 168MHz) as sysclock. 3) you use the transmit clock out of the SRC4392 as I2S clock in to clock the output stage of the I2S peripheral of the STM32F427. 4) The DAC connected in parallel to the SRC4392 on the same I2S. --EDIT: read what i was missing above. What I find interesting is that you have 32bit data but set     hdma_i2s2_ext_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; As the memory bus and internal memory are 32bit I'd at least try to set that to WORD and let the DMA do the conversion.

[miavenitoidee123]

Posted on July 11, 2014 at 17:27  Hi bs 1) SRC4392 can be set to run with 12.288Mhz or 24.576Mhz oscillator. The only thing depends is how you set the internal clock divider inside Port A/B by using I2C protocol. I have a crystal oscillator(TCXO 12.288Mhz)  which is connected to both SRC(slave) and STM(master) that generates MCLK. My issue is that TX stream gets out of sync. If i take SRC out of the picture and let only the MCU connected to MCLK i still get the TX stream out of sync after some time. So i don't have any issue with SRC chip. If you need help with configuring SRC i can help. I just need to make the MCU work properly first. 2) I am running same clock configuration as you are saying. Here is my clock configuration:

http://tinypic.com/view.php?pic=143ztec&s=8#.U7_67Ge_laR

The I2S DR  register is 16bit long so each channel has to do 2x16bit transfers. I tried Word setting on the DMA and did not work. But maybe i missed something. I will check again and reply. I also reconfigured and tested again without success the FIFO settings as follows: Threshold: Half full Data width memory and peripherial: half word Burst size: 4 increment Now I'm running full duplex master receive and 10hours have passed and it's stable. Can you tell me if you tried running any of STM32F4 MCU as full-duplex with external clock oscillator? and if you did can you confirm that your configuration is reliable for long term use?

[Tesla DeLorean]

Posted on July 11, 2014 at 17:51

The STM32 does resynchronize input signals, you could run the part off the TCXO clock too

[miavenitoidee123]

Posted on July 11, 2014 at 18:01

Hi clive

what do you mean?

you could run the part off the TCXO clock too

[Tesla DeLorean]

Posted on July 11, 2014 at 18:37

If you wanted a common clock domain, the STM32 can be clocked by an external 1-50 MHz source. Given the inflexibility in the clocking scheme within the device, this can be desirable to hit magic frequencies, or act as a master.

[miavenitoidee123]

Posted on July 12, 2014 at 14:33

You are right. I took this option as a backup.

However. Today I figured it out :) The ''shift'' problem is because of my power source. If I short-circuit the power for a very very short time before the voltage regulator I get to reproduce the scenario. At some point in time the power source(SMPS) is interrupting the current to the MCU. The capacitors hold the power for a short amount of time which causes the MCU to pause it's execution. Maybe at that point HSE is not oscillatiog anymore. After power is stabilized again the MCU continues the execution,  no reset is triggered, but it is too late. The I2S stream advances while MCU is in standby and there it's my WS vs DATA desync problem. A big capacitor 1000uF solved the problem. But I will replace the PSU soon. I will do some more tests. And i'll be back the conclusion or more questions. :)

[miavenitoidee123]

Posted on July 13, 2014 at 18:41

Ok, the problem continues.

The big capacitor added didn't solved the issue. The ''shift'' still occurs, but now I have to wait even longer to happen. But I'm on the right track. So there are two clock domains which needs to stay online: 1. HSE clock 2. I2S external MCLK input The DMA is the ''bridge'' between them. The problem after all  is not the power source. Is that the HSE PLL oscillator is loosing lock at some point in time for about 1-16fs. Thats's why when using PLL clock to fed I2S MCLK, the audio stream stays in sync forever(when HSE pauses, the internal I2S MCLK pauses too). Because my MCU is on a adapter board and I'm working with trough-hole parts, the crystal (8Mhz) is as close as possible to the chip(1.5cm) but not closer enough I think. To put crystal closer and add proper grounding to the current design is impossible. So now I'm thinking to replace the crystal,resistor and capacitors from the PH0/PH1 pins with a crystal oscillator(TCXO) and fed the signal to PH0 pin. I'm really optimistic that this will solve the problem for good this time. I will update soon about this...

[schauer]

Posted on July 14, 2014 at 17:26

I'm happy to read that you were able to make a few steps forward. The last day I had an issue with a permanent shift of 16bit to the right in the I2S stream.

I have a situation where the I2S stream is (possibly) restarted and after the second streaming start all data was shift right by 16bit. It helped me to reset the peripheral (via reset register) after stopping it and reconfigured it before starting again. I have the DMA configured to do the word <-> half word conversion with FIFO and SINGLE bursts (currently). This is acutally working without issues, I'm going to change to INCR4 anyway.

[miavenitoidee123]

Posted on July 14, 2014 at 19:35

Hi bs

How are you running the I2S port? master/slave? receive/transmit? Who is the second stream? You are running full-duplex? or both I2S ports? Are you running on internal or external clock for the I2S MCLK? Maybe you are having the same issue as I did. As I learnt my lesson. Left shift represent pin overdrive(probably on I2Sx_CK). Right shift represents HSE/AHB clock instability issue. Make sure none of this is happening. In 32bit data frame only half word works to the peripheral In my case only this options works for I2S: 1.half(peripheral) , half(memory), 4 increment 2.half(periph), word(memory), single But the 2nd option would keep the bus more busy. My problem got solved for good. I replaced the crystal with an external 25Mhz TCXO, changed the divider before PLL and switched to BYPASS mode. Now the HSE clock is stable.

[schauer]

Posted on July 15, 2014 at 15:30

I run the I2S2 port as follows:

- SPI2 part as Master Receiver - I2S2ext as Slave Transmitter The STM32 has a HSE quartz with 24MHz and the internal I2S PLL is fed with a 1MHz clock derived from the HSE. The I2S PLL out is output via the MCO2 pin to the SRC4392 and provides the master clock to it. The DMA's are configured as  - msize: word  - mburst: incr4  - with fifo  - psize: halfword  - pburst: single Currently runnning without issues since yesterday evening.