STM32F427 FMC connected SDRAM

[martinhaefner9]

Posted on November 17, 2016 at 12:16

Hi guys,

we have a IS42/45S16100H device connected to STM32 FMC bus ( BANK2 ).

If we run the application from internal SRAM everything is fine. Unfortunately, if we use the SDRAM as heap, we have trouble. Sometimes the embedded os tells us that some timer structures are invalid, sometimes it ends up in a hardfault. Restored LR and PC are shwoing nonsense. This is the timing we set up for the SDRAM   FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;   /* TXSR: min=70ns (6x11.90ns) */   FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;   /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */   FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;   /* TRC:  min=63 (6x11.90ns) */   FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;   /* TWR:  2 Clock cycles */   FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;   /* TRP:  15ns => 2x11.90ns */   FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;   /* TRCD: 15ns => 2x11.90ns */   FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; /* FMC SDRAM control configuration */   FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;   /* Row addressing: [7:0] */   FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;   /* Column addressing: [11:0] */   FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;   FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;   FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_2;   FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;   FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;   FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;   FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_Disable;   FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;   FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;

Refresh count is set to 1290.

Any ideas ?

Kind regards

Martin

[waclawek.jan]

Posted on November 17, 2016 at 13:03

Have you read the errata?

JW

[martinhaefner9]

Posted on November 17, 2016 at 13:47

Hi, thanks for your reply.

We checked the errata. CPU revision is ''3''. I also enabled the RBURST to avoid corrupted data at the end of an SDRAM row. I guess that's all concerning SDRAM. Regards Martin

[martinhaefner9]

Posted on November 18, 2016 at 08:31

hi guys,

we found out that the problem maybe is in the st' hal. In there the timings for RowCycleDelay,RPDelay, RCDelay are only set for the FMC_Bank_1. If we set this also for BANK 2 everything seems to run quite well. But, in the Datasheet there is a note that the registers in the FMC_SDTR2 are don't care ? What is correct ? Can somebody confirm that this is an issue this is the code which is running:   if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )   {     tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);                          FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;   }   else   /* SDTR ''don't care bits configuration */   {     tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);                  tmpr4 =   (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);                          FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;             FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;   } Thanks again. Martin

[martinhaefner9]

Posted on November 18, 2016 at 09:57

We got it now.

ST forgot to set a value in bank2 timing config. See red marked line ( that was missing before )  if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )   {     tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);                          FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;   }   else   /* SDTR ''don't care bits configuration */   {     tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |            

(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);

                 tmpr4 =   (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);                          FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;             FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;   }

[slimen]

Posted on November 18, 2016 at 13:08

Hi,

Which HAL version are you using ?Ensure that you are using the last version of STM32CubeF4 v1.13.0 which contains bug fixes and enhancement.Regards