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STM32F410 PLL Jitter on PWM

Associate III


i want to use a really precise PWM signal but i get a lot of Jitter on it.

I am using the F410 with a 16Mhz crystal. The PLL produces from there a Frequency of 100Mhz (I need this high frequency for my other tasks).
The rest of my hardware needs one PWM signal with 1kHz and a 5ms on time. So i use a PWM Timer for that.
The problem now is, that the edges of this signal have a lot of jitter, around 3ns both on the on-time aswell on the period.
If i deactivate the PLL and directly use the 16MHz crystal for comparison, the jitter is much lower, around 0,5ns.

In the datasheed of the uC is a Table 44 about the Main PLL characteristics and in there is the Jitter with +-150ps much lower. As i see it, the chip has no option to add a external VCO-capacitor to the PLL.
Do anyone know, where this differences between datasheet and hardware come from and how can i fix this?

Best regards,
Philipp Diehl


Mhm ok so you think i should live with this?

Associate III

Technically my "breadboard" has the same jitter as the nucleo but repeatability i switched here to the nucleo.

I have only the circuit diagram, no layout so i can`t say something about that. Do you know where i can get those?

use crystal as clock - if possible (max. 50MHz using external oscillator );

if needing pll , crystal source... better not possible in this case.

but from data -- jitter not sooo bad here , F411 :



or try other chip , i use H743 and here pll seem better...

or (as i did) with DAC, set DAC as I2S master with his own oscillator, optimum performance.

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ST Employee

Hello @PDieh.1

I propose trying these steps in your jitter measurement: 

1. Configure your scope to measure all the sampled clock periods instead of just the first clock

2. Configure your scope to capture multiple periods on the screen

3. Record mean, standard deviation, and the peak to peak values 

4. Repeat steps 2 and 3 25 times

Then we'll compare our results, I did those tests and the jitter looks okay (I used a scope with 50Gsa/s)  

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I guess your oscilloscope sampling frequency from your jitter information.
because there are no another stuff on your system can be operate over 200MHz which it can be make some jitter under 5ns so your jitter less than 3ns that it may make by another stuff.

and the other condition is jitter behavior is only the edge of pulse which it can be make by 2 causes (that I known)
1. Indicator sampling - your AC Isolate, it reduce noise from other switching device on AC Line but it's no effect with own switching -> your should try to use differential probe with isolate GND between your indicator and device. I guess your will got more perspective.

2. device supply do not fast enough to recovery voltage - which this condition has 2 places first is internal regulator in stm32 and the other one is regulator supply on board.
but if this condition is root-cause, you should test by run switch many GPIO and you will see another jitter on same GPIO too because it's use same regulator.
- for this condition I think a IC buffer that support more speed than stm32 GPIO may can help to reduce this.

Lucky be with you.

Hello @Sarra.S ,

Sorry for the late answer, but i am not really sure what you mean with the first step.
What are all the sampled clock periods?

Associate III

Hello @Sarra.S 

Can you please explain, what you mean with that?