Posted on November 26, 2017 at 17:07Dear all,
I'm an Engineering student who's trying to learn the Embedded programming with STM. Kindly tolerate my ignorance.
I've read the reference manual (ADC) and the data sheet of the specified Kit and I have the following queries:
1. ADC Clock:
The ADC features two clock schemes:
a) Clock for the analog circuitry: ADCCLK, common to all ADCs
This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at fPCLK2/2, /4, /6 or /8.
b) Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be
enabled/disabled individually for each ADC through the RCC APB2 peripheral clock
enable register (RCC_APB2ENR).Q1: For a real time signal acquisition (for e.g., biosignal), I understand that the scheme a) should be used. But, in what circumstances, the scheme b) shall be used?
Q2: From the architecture diagram, the ADCCLK is derived from APB2 clock with a Prescalar. What exactly is the value of APB2? What is the code snippet that could give me the value of any of these clocks? [I am sure RCC header file is used]
I've read that 'The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz'
Q3: Assuming that APB2 clock is the low-speed one which is 42MHz, I also read that the Max ADC clock can be 30MHz (for the voltage range 2.4 to 3.6v) which means, a prescalar of minimum 2 should always be set, isn't?
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOC, ENABLE); // 168MHz DMA
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); //42MHz ADC (?)
ADC_CommonInitStructure.ADC_Mode =ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_Prescaler =ADC_Prescaler_Div2; // 21MHz ADC (?)
Thank you for your time and help.
#kit-stm32f4-discovery ##stm32f4 #adc-clock
