STM32F407I with LQFP176 RTC registers resets when Vbat below 3.1V

[c2]

Posted on April 21, 2015 at 15:18

Hi everyone.

In a new development with STM32F407I i have some problems with backup domain especially with internally switch Vdd/Vbat to backup domain.I use a CR3032 backup battery ( 3V lithium ) connected to Vbat pin via a BAT48C double Schottky diode and 1uF cermet cap directly on Vbat pin, second part of this diode is connected to Vdd 3,3V.Pin PDR_ON is connected to VDD 3,3V.  ADC is running with separate 3.3V, Vref is also external 2.5V, so all voltages are generated separately from one main voltage.VDD analog and Vref voltage needs more time to go to 0V as Vdd after power down.After power down ( switch off main voltage) and power up all registers of  RTC are lost. If cap of Vbat pin is increased to 470uF ( and charged via BAT48C to 3.3V VDD ), i can see after power down that LSE assigned to RTC stops working when Vbat drops after approx. 60 sec. below 3.1 Volts, and after powering up all registers of RTC are lost.The measured current in to Vbat pin with PDR_ON connected to VDD is in power off state approx 2uA ( when Vbat is above 3.1V), this is ok, when Vbat drops below 3.1V also current drops to approx. 0.1uA. When  PDR_ON  is connected to VSS, there are no problems with backup domain after switch off, Vbat can go below more then 2V without loss of datas. But there is another problem with current: in this case the Vbat current is near 2mA, so battery will be discharged rapidly.I use PC13 as  standard input, PI8 is not connected, PA0 is used as an analog input to ADC,  PC14 PC15 is connected to a 32kHz Osc., RTC uses this as LSE. Setup of RTC shall be ok and RTC works fine, no wakeup or tamper pin is assigned to RTC, buffered RAM is not used.I have built two prototypes and both shows the same behavior.Other types of STM32F407 with 144pin or 100pin LQFP in other developments works fine with same hardware setup, also the software setup of RTC is the same.I didn`t found any restrictions to battery voltage in the data sheets, 3.0V shall be good.Is there anyone with the same problem and has found the cause or a solution?What is about the power down reset to backup domain described in data sheets? It shall be only when BOTH Vdd and Vbat where at the SAME time low?Greetings and thanks for every idea!Chrisi #stm32f407-vbat-backup-domain-rtc

[waclawek.jan]

Posted on April 21, 2015 at 23:07

> When  PDR_ON  is connected to VSS, there are no problems with backup domain after switch off, Vbat can go below more then 2V without loss of datas.

> But there is another problem with current: in this case the Vbat current is near 2mA, so battery will be discharged rapidly. The datasheet specificaly prohibits using VBAT with PDR_ON not connected to VDD, at least on two places. > VDD analog and Vref voltage needs more time to go to 0V as Vdd after power down. That sounds like a potential problem, too - datasheet requires VDDA and VDD difference never to exceed 300mV. > Other types of STM32F407 with 144pin or 100pin LQFP in other developments works fine with same hardware setup, Then try to spot all the possible differences and try to make the current circuit as similar as the 144/100 pin ones are, including the internal connections in the 100/144 pin packages. JW

[c2]

Posted on April 22, 2015 at 11:31

Dear Jan, thank you for your response.

after exploration there is following behavior:switching on: Vdd rises faster than Vdd analog or Vref: no matterswitching on: Vdd rises slower than Vdd analog or Vref: no matterswitching off: Vdd decreases slower than Vdd analog : no matterswitching off: Vdd decreases faster than Vdd analog: problem occurs!in this case: Battery CR2032 ( internal resistance 10 Ohm)  with capacitor more then 100uF parallel to ceramic cap 1uF: problem occurs, if voltage drops below 3.1V (time independ, can be after 1 hour after switching off), LSE stops working and data loss in backup domain.also in this matter: use of an external power supply connected to battery holder, Voltage 2.9V : no problem!There must be a very short and hard current inrush to Vbat during switch off, so battery + cap can`t handle it. external power source can handle it.Workaround: a Schottky diode between Vdd and Vdd analog, cathode to Vdd:VDD discharges Vdd analog with a difference of 0.2V during switch off. --> no problem with battery and backup domain!Dear ST, if you read this: it makes sense to split VDD digital and VDD analog, als Vref.There is much more analog parts around of controller, to avoid drifts in voltage dividers and so on it makes sense to make a very accurate VDD for analog parts. Depending on topology it is not easy to bring up or down different power rails at exactly the same time!It is easier to create a Vbat pin with a wired diode ''OR'' to Vdd and Vbat, behind this ''OR'' there can be different power gates for to switch on/off parts of backup domain, no problem!But what shall this with this mystical ''power switch for backup domain'' including PWR_ON pin? Power reset pin shall be power reset pin and no more.Or maybe it is a good idea to spend three or four transistors more of this million transistors to avoid this inacceptable behavior?To Jan: Thank you for your ideas, at no time I had brought in touch  a function of Vdd analog with the unusual behavior from Vbat power switch! One week wasted!Greetings and thank you for your ideas!Chrisi

[waclawek.jan]

Posted on April 22, 2015 at 17:57

> switching off: Vdd decreases faster than Vdd analog: problem occurs!

> There must be a very short and hard current inrush to Vbat during switch off, so battery + cap can`t handle it. external power source can handle it. What IMO happens here is, that while VDDA is higher than VPOR/PDR(falling), the internal VBAT switch is on, so if VDD is lower than the regulator voltage, the whole digital circuit starts to be supplied from VBAT. JW

[stst9184]

Posted on October 28, 2015 at 18:41

How did you stimulate these cases?

... switching on: Vdd rises faster than Vdd analog or Vref: no matter switching on: Vdd rises slower than Vdd analog or Vref: no matter switching off: Vdd decreases slower than Vdd analog : no matter switching off: Vdd decreases faster than Vdd analog: problem occurs! ... Can you tell more about it?