STM32F407 Timer2 trigger ADCs and then DMA to SRAM problem

[gavinli]

Posted on October 22, 2014 at 21:36The original post was too long to process during our migration. Please click on the attachment to read the original post.

[Tesla DeLorean]

Posted on October 22, 2014 at 22:40

Not sure I have the time/resources to wade through this.

I will observe that ''common'' stuff on the ADC should be done ONCE only. You don't use EOC on the ADC, the DMA eats this, you should really use the DMA HT/TC to signal the end-of-conversionS

[gavinli]

Posted on October 23, 2014 at 00:23 It seems only ADCs can only trigger DMA2, not DMA1. I changed all DMA1 in my code to DMA2 and everything start working. I also did a change to use DMA_PeripheralDataSize_HalfWord and  DMA_MemoryDataSize_HalfWord instead of DMA_PeripheralDataSize_Word and DMA_MemoryDataSize_Word, it seems the program also works correctly. I don't understand why. Clive1, You said I should use DMA HT/TC interrupt. But what is the purpose? I don't do any data processing in the DMA ISR, why do I care the HT/TC interrupt? I am also confused about the data in my buffer. Is it arranged as: ADC1.scan1, ADC2.scan2, ADC3.scan3, ADC1.scan2, ADC2.scan2, ADC3.scan2,... Or, Is it arranged as ADC1.scan1, ADC1.scan2,...ADC1.scan8,ADC2.scan1, ADC2.scan2,...ADC2.scan8,ADC3.scan1, ADC3.scan2,...ADC3.scan8? Please help explain.

[Tesla DeLorean]

Posted on October 23, 2014 at 00:41

APB2 peripherals use DMA2, APB1 use DMA1, the ADC are on APB2. The Reference Manual describe the DMA unit, channel, stream relationships.

The TIM triggers the ADC (24 Samples), the ADC triggers the DMA, the DMA can be used to generate the equivalent to the EOC. I would NOT use the TIM or ADC IRQ Handlers. The buffer you would expect is ADC1.1, ADC2.1, ADC3.1, ADC1.2, ADC2.2, ADC3.2, ADC1.3, ... ADC3.8 If you have a buffer holding 48 samples, you'll get a DMA HT interrupt once the first 24 samples complete, and the TC when the second set of 24 samples complete. You'd do this so your sample set would be static and contemporaneous while the next set fills.

[gavinli]

Posted on October 23, 2014 at 16:49 Thanks Clive1. I misunderstood the HT/TC to be the FIFO inside DMA. Now it make sense that they are for my buffer. I still have two questions: 1. I am using ADC_TripleMode_RegSimult mode + ADC_DMAAccessMode_1, so I guess the trigger sequence is T2->ADC1->ADC2->ADC3->DMA2_Stream0. ( my code works with DMA2_Stream0_IRQHandler). According RM0090 Rev7 page 401, the DMA mode1, I should use ADC3 to trigger DMA2_Stream2(RM0090 Page305, Table43), But why this not work? 2. If I have 4 channels to scan in ADC1, and 4 channels to scan in ADC2 and 8 channels to scan in ADC3,  then I should set DMA_InitStructure.DMA_BufferSize = 4+4+8; Is it right? (assume I have long enough T2 trigger period). Thanks again

[Tesla DeLorean]

Posted on October 23, 2014 at 17:38

When data is funnelled out the ADC Common Data Register in Dual or Triple modes then ADC1 is controlling, and it's DMA. You want to configure all ADC symmetrically otherwise you're going to have a lot of headaches.

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