STM32F407 Timer2 trigger ADCs and then DMA to SRAM problem
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‎2014-10-22 12:36 PM
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‎2014-10-22 1:40 PM
Not sure I have the time/resources to wade through this.
I will observe that ''common'' stuff on the ADC should be done ONCE only. You don't use EOC on the ADC, the DMA eats this, you should really use the DMA HT/TC to signal the end-of-conversionSUp vote any posts that you find helpful, it shows what's working..
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‎2014-10-22 3:23 PM
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‎2014-10-22 3:41 PM
APB2 peripherals use DMA2, APB1 use DMA1, the ADC are on APB2. The Reference Manual describe the DMA unit, channel, stream relationships.
The TIM triggers the ADC (24 Samples), the ADC triggers the DMA, the DMA can be used to generate the equivalent to the EOC. I would NOT use the TIM or ADC IRQ Handlers. The buffer you would expect is ADC1.1, ADC2.1, ADC3.1, ADC1.2, ADC2.2, ADC3.2, ADC1.3, ... ADC3.8 If you have a buffer holding 48 samples, you'll get a DMA HT interrupt once the first 24 samples complete, and the TC when the second set of 24 samples complete. You'd do this so your sample set would be static and contemporaneous while the next set fills.Up vote any posts that you find helpful, it shows what's working..
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‎2014-10-23 7:49 AM
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‎2014-10-23 8:38 AM
When data is funnelled out the ADC Common Data Register in Dual or Triple modes then ADC1 is controlling, and it's DMA. You want to configure all ADC symmetrically otherwise you're going to have a lot of headaches.
Up vote any posts that you find helpful, it shows what's working..
