stm32f4 TIM2 multiple channel input capture

[EPora.1]

Hello,

I'm trying to write a PWM input capture function(I only need the on time. not the frq and duty cycle) and I see that it takes two channels of a timer. I need to use all four channels, Is it possible?

Thanks

[rpip.1]

you can cofigure ch1 to falling edge capture. And make slave mode of TIM to reset triggered by TI1F_ED. There falling and rising edge will reset TIMER, but capture only happen in falling edge.

[waclawek.jan]

Yes.

You can use only one channel for one signal, detecting both edges in one channel, if you are sure that the edges are far apart, enough for each individual edge to be handled (probably by interrupt). This may be good up a few kHz, with both positive and pulse widths somewhat below 1ms; the exact number depending on the latencies you can achieve.

You could improve things by one order of magnitude or maybe better, using DMA, if your STM32 model has individual DMA channels for each TIM channel; but there I definitively would *not* recommend capturing on both edges, i.e. using one channel per signal, as it's tricky to distinguish the rising and falling edges afterwards.

JW

[EPora.1]

Thanks for your comment.

The use of it is reading some around 700hz PWM signals. If I have understood correctly I should set an interrupt for rising and falling edge of the channel and reset the timer in the rising, then read the value in the falling edge. correct?

[rpip.1]

you don't need an interrupt. Reset is triggered by ED signal automaticlly. CCR1 can capture falling edge automaticlly. Read CCR1 with a freq over 700hz will not miss any data. nothing but I don't know what other three channels do. they maybe influenced by reset.

[EPora.1]

yes it may be a problem. but all channels are coming from the same source which is an RC receiver so maybe it gives all the data at the same time.

[waclawek.jan]

Yes, that's what @rpip.1​ suggested above and is a neat trick indeed; but that is good only for one channel per timer, plus there's a small delay between the actual edge and reset which ST does not care to specify, one or two timer clock cycles.

JW

[S.Ma]

If the timer has multiple uses, use it free run with overflow and any edge capture interrupt which save the value and pin level, comparre with previous measurement and deduct high level. Then add a sw patch in case the signal is cut or too low frequency. This way the other timer channels are free fir other use.

[EPora.1]

That is possible but I wanted to know if there is a hw solution like the PWM output.

[rpip.1]

you can cofigure ccr1~4 to both edge sensitive capture as @waclawek.jan  said.

All you need is an interrupt much over 700hz. you can do some calculate without reset timer.

for example, channel 1. you read CC1IF in TIM2->SR, if it's set, then you read the correspnding IO level in GPIO->IDR.

if IO is set, then R_data = TIM1->CCR1, if IO is reset, then F_data = TIM1->CCR1. then you just need to minus R_data from F_data.

Be careful with the overflow of TIM. And if CC1IF is not set, you must not read ccr1 in case of flag is cleared by reading,