1 ACCEPTED SOLUTION
Accepted Solutions
> How would the BOOT1 option bit be set?
The nBOOT1 option bit is within the option bytes. Use STM32CubeProgrammer to set the option bytes. Connect and select the "OB" tab.
> - In the datasheet, Table 21 states there can be a maximum V_DD-V_DDA voltage difference of 0.4 V. All my analog inputs can output a maximum of 2.0 V, and ideally I would like to power the MCU with 3.3 V. Would there be issues with these voltages, as it exceeds the 0.4 V limit? If so, would it be better to increase the V_DDA, or decrease the V_DD to be around 2.4 V? I am concerned about any issues with the MCU at this lower voltage. Likewise, how would the V_REF+ be affected in this situation.
Per the datasheet, VDDA = 2.0 and VDD = 3.3 doesn't work due to the restriction you found. You can reduce VDD without affecting much except the chip will not be able to run as fast. If max clock speed is a priority, keep it at 3.3V.
Generally it's not tenable to supply VDD and VDDA separately due to this, but it can be done if the restrictions are followed. Easier to put a ferrite bead before VDDA and connect them to the same supply.
VREF+ is separate from VDDA but also must be within 0.4V of VDDA.
For your application, two options:
- VDD = VDDA = 3.3 V will give higher possible clock speeds but generally worse analog performance due to only using a portion of the overall range.
- VDD = VDDA = 2.4 V (or so) will give better analog performance but lower max clock speeds. You will also need to ensure external signals are compatible with 2.4 V logic rather than the more common 3.3 V.
> How would the BOOT1 option bit be set?
The nBOOT1 option bit is within the option bytes. Use STM32CubeProgrammer to set the option bytes. Connect and select the "OB" tab.
> - In the datasheet, Table 21 states there can be a maximum V_DD-V_DDA voltage difference of 0.4 V. All my analog inputs can output a maximum of 2.0 V, and ideally I would like to power the MCU with 3.3 V. Would there be issues with these voltages, as it exceeds the 0.4 V limit? If so, would it be better to increase the V_DDA, or decrease the V_DD to be around 2.4 V? I am concerned about any issues with the MCU at this lower voltage. Likewise, how would the V_REF+ be affected in this situation.
Per the datasheet, VDDA = 2.0 and VDD = 3.3 doesn't work due to the restriction you found. You can reduce VDD without affecting much except the chip will not be able to run as fast. If max clock speed is a priority, keep it at 3.3V.
Generally it's not tenable to supply VDD and VDDA separately due to this, but it can be done if the restrictions are followed. Easier to put a ferrite bead before VDDA and connect them to the same supply.
VREF+ is separate from VDDA but also must be within 0.4V of VDDA.
For your application, two options:
- VDD = VDDA = 3.3 V will give higher possible clock speeds but generally worse analog performance due to only using a portion of the overall range.
- VDD = VDDA = 2.4 V (or so) will give better analog performance but lower max clock speeds. You will also need to ensure external signals are compatible with 2.4 V logic rather than the more common 3.3 V.
