STM32F303 maximum ADC sampling rate

[Mercadei]

Hi everyone,

I am currently looking into the STM32F303CCT6 and I'm a bit confused by the ADC specifications. ST's website mentions it can achieve up to 18 MSPS in interleaved mode. However, looking through the Datasheet and the Reference Manual (RM0316), I don't see a clear way to hit 18 MSPS at 12-bit resolution.

I realize the hardware interleaved mode is only dual (e.g., ADC1/2 and ADC3/4). Since the documentation mentions dual mode can reach up to 9 MSPS at 12-bit, and there is no native quad-interleaved mode, I suspect one of two things:

1. There is a way to manually coordinate the two dual pairs (using all 4 ADCs) to reach 18 MSPS at 12-bit.

2. The 18 MSPS claim strictly refers to running a dual interleaved setup at a reduced 6-bit resolution.

I would deeple appreciate some insight regarding if 18 MSPS at 12-bit is actually possible on this MCU, or if I am limited to the dual mode specs?

Thanks in advance!

[mƎALLEm]

Hello @Mercadei and welcome to the ST community.

There is no “Quadruple” mode available. Only Dual mode. Where:
ADC1 is a master and ADC2 is its slave. 

ADC3 is a master and ADC4 is its slave.

Not possible to synchronise all the ADCs as in quadruple mode. So not possible to reach 18MSPS at 12 bit resolution.

[AScha.3 · Accepted solution]

Hi,

as @mƎALLEm explained, no "quadruple mode" .

But you could try: 

- set all 4 ADC to max. speed settings (sampling time, one ch conversion), on trigger mode

- set TIM1 to 144 MHz ; use 4 signals (TRG, TRG2 ; compare 2 , 3 ) as start/trigger for the 4 adcs

- set for all adc DMA channels

- now , set/separate the delays to equal values, so starting the timer giving a sequence of triggers 

Should work, to get a combined sample rate of 18 Msps.

With little overclocking:

At 80M core, 160M on TIM1 , ( arr 32 ) with 8 ticks spacing between triggers, could reach 20 Ms.

[Mercadei]

Hello all,

Thank you both for your answers, and apologies for the delayed response, I wanted to test the HW before getting back to you.

After a couple tests with the NUCLEO-F303RE DK, I managed to achieve a clean and stable 18 MSPS at 12-bit resolution by synchronizing the four ADCs independently (just as @AScha.3 said).