STM32F217 HSE and Timer Sync

[PCarn.1]

I'm working with an STM32F217 and I have a few timer channels setup as sync clocks to regulators (around 1.5 MHz). I'm checking to make sure my sync lines are actually using HSE as a reference clock by looking at the phase drift between my external oscillator output and an STM32 timer output on an oscilloscope. With the amount of drift I'm seeing it doesn't seem like the timers are referencing HSE. I'm confused though because bits 3:2 of RCC_CFGR say I'm referencing my external oscillator as my system clock.

Here are the related register values:

RCC->PLLCFGR = 0x24403c18

RCC->CR = 0x30b6983

RCC->CFGR = 0x940a

[tjaekel]

I guess, the OP wants to illustrate just what he wants to see (an explanation animation from somewhere).
Actually, this animation is not appropriate to the topic: it shows you a tiny difference in frequency (therefore the phase is drifting).

A phase offset is constant (between two clocks) or it has jitter (than it jumps back and forth but never matching again with a clock cycle difference because it is slower as the other one).

Why he is asking, I guess: how wants to get a phase lock between external HSE clock and a TIM generated clock (deep inside MCU generated, after all PLLs, clock trees...).

And my answer (as yours) would be: NO WAY! If a PLL generates another clock, even with the "same" frequency - they will never be in a "predictable" phase lock (it can be random when the phases look "looked"), neither a stable phase correlation (the PLL is "breathing" a bit).

The only way is to consider the phase relation after the PLL has generated the clocks (PLL out), and they never go again through a PLL, just via DIViders etc.). The PLL "decouples" the external HSE oscillator from the rest of all clocks.

[AScha.3]

NO !

Just think: "PLL" is --- what ?    PHASE Locked Loop .

So a good (correct working) PLL has a fixed relationship for in and out going frequency , and fix phase relationship.

If not - its not "locked" (phase-locked (!) is exact definition) and bad design.

How our famous STM products do here ?

All theory is gray - so lets check on H563 nucleo board :  8MHz HSE (from st-link) , on H563 -> MCO (100MHz PLL/10 -> 10MHz out (yellow))

Screenshot is overlay from many traces (50 or so, set screen persistence > 0,5 sec);

so can see fixed and constant relation from (triggered) blue 8MHz to (untriggered) yellow 10MHz.

What we really can see here: how good or bad is the PLL design, giving some more or less jitter;

here clear below 1 ns , so with this fast and dirty check indicating : fine PLL design.

ed

And here -just for fun-  setting PLL to even factor, to get 16MHz on mco:

(also many traces overlay) See fixed phase and frequency relationship. :)

[PCarn.1]

Sorry the gif doesn't render as expected. If you click on it so it opens in a new window it should work properly.