2016-01-04 06:59 AM
Hi,
I was hoping that I might get some clarification regarding the EXTI on the STM32F207. Looking at Fig 4 (STM32F20x block diagram) within the datasheet, it would appear to be APB2; this seems to be further confirmed in section 8.2 of the reference manual.
When HAL_GPIO_Init() is called and the EXTI is configured the __SYSCFG_CLK_ENABLE(); macro is called which sets the SYSCFGEN bit within the RCC_APB2ENR register. To confirm my understanding I called __SYSCFG_CLK_DISABLE(); before entering a while loop (which just sits waiting for an interrupt from a button press) my expectation was that the interrupt would not kick, but it did and now I’m confused.
My confusion might be fuelled by this being the 1st day back after the holidays, but after trawling through a variety of google searches I couldn’t find anything that explains why this is occurring. If polling the button press I clearly need the GPIOxEN bit set within RCC_AHB1ENR register to detect the state change so am I looking at the wrong clock?
Thanks.2016-01-04 10:28 AM
If you want to disable the interrupt do so via the EXTI or the NVIC
The GPIO pin and it's functionality will go through the AHB clock for the bank. The pin synchronizer and IDR, ODR, etc and the peripheral use that clock. The EXTI/SYSCFG clock relates to the registers and configuration of that peripheral, but it would surprise me if this impacted the state of the enable bits passed to the GPIO bank(s). Remember turning off the peripheral clock doesn't disable the registers/outputs, just your ability to communicate with it over the APB, or change them. You'd have to find someone familiar with the IC design, to get an exact answer, and I doubt you'll find those guys here. What exactly is the problem with enabling both the SYSCFG, and GPIOx clocks?2016-01-05 01:09 AM
Thanks for the response. I had at the back of my mind that the SYSCFG clock was purely for configuration purposes, but couldn’t find anything indicating an alternative for when it was operational.
The question stems from me currently allocating pins on the MCU to provide the system’s functionality. Driving this is the requirements of the Safety Manual (UM1845) and the How to achieve the lowest current consumption with STM32F2xx (AN3430).
The Safety Manual requires me to implement a 1oo2 scheme by connecting any external safety-relevant signal to two independent GPIO lines, which also includes interrupts. AN3430 recommends that the GPIO clock can be disabled one a peripheral is configured if the isn’t a read or write from/to the GPIO registers, thus providing a power saving.
So in the process of trying to allocate appropriate pins and make controlling clock states as manageable as possible I determined that the GPIO clock wasn’t required to be enabled to detect an interrupt. Subsequently, I wanted to understand which clock was required and this is where I drew the blank.
Would this be a question better directed at ST themselves?
2016-01-05 03:48 AM
I'm not sure if I understand your question completely, but...
For power saving purposes, I have the impression that there is unclocked circuitry in the IO ports of STM chips that allows raising an interrupt. This allows EXTI to wake up the processor from deep power-save states where clocks are turned off.2016-01-05 06:16 AM
The thought had crossed my mind that it might be the case, I don’t suppose you have a reference do you?
Given that all the other peripherals that I’m using have a peripheral clock associated with them I assumed that there would be an underlying clock for the EXTI. I’m now almost convinced that there isn’t, unless it is the system clock. However, the Reference Manual isn’t providing me with any answers so now I’m just left with a question mark as to how it works.
2016-01-05 09:56 AM
If you can't quickly find a clock for EXTI, it doesn't have one. Sounds plausible. EXTI is just a few extra logical ports in each GPIO module. And IIRC the registers are also found inside another module, correct?
2016-01-06 01:13 AM
Sorry, what do you mean by found inside another module? Other than the system configuration register?
2016-01-09 11:48 AM