Posted on October 28, 2011 at 12:00I have just tested my second design with STM32F2, now it is STM32F207ZFT6, the ADC behaviour is the same as in my first application - strong noise in ADC signal.
Essential part of the board schematics :
http://www.sendspace.com/file/si46gl
Board photo :
http://www.sendspace.com/file/45n68v
Noise of current input without any signal connected :
http://www.sendspace.com/file/totkwn
The same input noise with the CPU analog pin shortcircuited to GND :
http://www.sendspace.com/file/cjagfy
Note : In the signal graphs above, the vertical axe is in ADC-bits, not in volts!
; don�t be confused by its legend �[V]�, for this test we have used our modified program to see rough ADC data.
There are permanent spikes over 30 LSBs and more in the sampled signal, although they shouldn�t exceed 5-10 LSBs, by my opinion.
Another details :
2-side PCB, on the bottom side there are another connections but most of it is poured with GND signal - common for both digital and analog, the analog ground is not separated. As the board consumption is minimal, below 100 mA, I think it should not cause such noise.
voltage reference VREF 3.3V buffered by opamp, blocked by 100nF and tantallum 10uF in parallel, the same with VREF/2; each of the processor power pin is blocked with 100nF cap
- in our older application we used the same design concept, but the processor used was AduC834; it has 12-bit ADC too and the signal noise was several LSBs only, there were no problems; main difference was that the AduCs internal voltage reference was used, no external one
- we have tested to disconnect processor analog ground pin from the board common GND and to connect it with extra wire directly to the voltage reference VREF ground, no effect
- it is three-phase network measuring device, there are 3 analog voltage channels and three current channels with switchable gain preamplifier; the CPU oscillator 25 MHz, internal clock 120 MHz by PLL, ADC-clock is 30 MHz(in compliance with techspecs), we have tested to slow main internal clock (therefore all secondary clocks too) downto one quarter, but without any effect
- ADC samples periodically input signal with rate 128 conversions per 50 Hz network period, i.e. each 156 usecs; results are transferred by DMA into internal RAM; data from the RAM are transferred via insulated RS485 (on another board) and visualized in our program. We have tried to prolong conversion times to maximum, no effect
- excluding CPU, there are only
3 opams, 2 analog switches, I2C thermometer and three ULN-switches(unused during test), powered by linear LF33 stabilizer, normally powered by 5V DC from switcher on another board, but during the test the switcher was disconnected and the LF33 was powered from clear laboratory 5V DC supply. I am sure nothing but the processor oscillator can oscillate on the board.
checking the signal with oscilloscope doesn�t get decisive results, the signal is too weak
Anybody with this processor family ADC performance experience
?
#stm32f2-stm32f4-a/d-noise #adc-noise
