stm32f103re EXTI interrupt response time

[trisf]

Posted on December 01, 2011 at 06:29

First of all sorry for English and messy explanation.

One of EXTI channels configured as interrupt on falling edge. EXTI ISR  toggles GPIO(set/reset) pin and resets EXTI pending bit. I measured time between these 2 events EXTI_6 falling edge and GPIO rising edge. And the fastest time I get with IAR toolchain (high speed optimization) is ~ 360ns. The question is - Why does it takes so long(~26 cycles)? Code example &sharpinclude ''stm32f10x.h'' EXTI_InitTypeDef    EXTI_InitStructure; NVIC_InitTypeDef    NVIC_InitStructure; GPIO_InitTypeDef    GPIO_InitStructure; void EXTI9_5_IRQHandler(void); int main(void){     __disable_irq();     RCC_PCLK1Config(RCC_HCLK_Div1);   RCC_PCLK2Config(RCC_HCLK_Div1);     RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO ,  ENABLE);     GPIO_InitStructure.GPIO_Pin =   GPIO_Pin_6 | GPIO_Pin_7 ;   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;     GPIO_Init(GPIOB, &GPIO_InitStructure);     GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_1 ;   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP ;   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz ;     GPIO_Init(GPIOA, &GPIO_InitStructure);     NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);     NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;   NVIC_Init(&NVIC_InitStructure);   GPIO_EXTILineConfig(GPIO_PortSourceGPIOB , GPIO_PinSource6 );   EXTI_InitStructure.EXTI_Line = EXTI_Line6;   EXTI_InitStructure.EXTI_LineCmd = ENABLE;   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling ;   EXTI_Init(&EXTI_InitStructure);        GPIOA->BSRR = GPIO_BSRR_BR1 ;   __enable_irq();   while (1){   };   }; void EXTI9_5_IRQHandler(void){     GPIOA->BSRR = GPIO_BSRR_BS1; //  PA1 set   GPIOA->BSRR = GPIO_BSRR_BR1 ; //  PA1 reset   EXTI->PR = EXTI_Line6 ; }; First strings of IRQ Handler in assembler I`ve got from compiler         SECTION `.text`:CODE:NOROOT(1)         THUMB //  111 void EXTI9_5_IRQHandler(void){ //  112    //  113   GPIOA->BSRR = GPIO_BSRR_BS1; //  PA1 set EXTI9_5_IRQHandler:         LDR.N    R0,??DataTable1_3  ;; 0x40010414         MOVS     R1,♯+2         STR      R1,[R0, ♯+1020] #strm32f103re-exti

[Tesla DeLorean]

Posted on December 05, 2011 at 17:09

Your words almost persuaded  me  that measured values are quite normal.

Well I'm certainly not sure they are outside what I might expect. If I want predictable, sub micro-second signalling, I'd be using hardware to achieve that placement. I'm also certain I could contrive some tests where it would get significantly worse timing.The thing is that STM does not mention all these aspects in their documentation (or I couldn`t find it). Like how many APB cycles does it take signal to pass from pin to NVIC via EXTI or latency of other interrupts from peripheral devices? I agree there are some things lacking with the documentation, but realistically some of this detail would need to come from a through understanding of the M3 core itself and it's interactions with the AHB, and APB buses. And that would come via ARM documentation and models. Definitely a matrix illustrating various peripheral, and where their speed deviates from nominal would be very useful. For example the AHB CRC register takes four AHB cycles. Basically the stuff that STMicro brings to the party, and less of what ARM does. At the end of the day, we all have to do our own due diligence, and test the device as we're actually using it.