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trisf · 2012-09-13

Posted on September 14, 2012 at 07:26Silly question Can I use external clock source (RCC_CR HSEBYP=1, HSE=1 ) to drive PLL?

trisf · 2011-11-30

Posted on December 01, 2011 at 06:29First of all sorry for English and messy explanation. One of EXTI channels configured as interrupt on falling edge. EXTI ISR toggles GPIO(set/reset) pin and resets EXTI pending bit. I measured time between these ...

trisf · 2012-09-17

Posted on September 18, 2012 at 06:54Thank you Clive.

trisf · 2011-12-05

Posted on December 05, 2011 at 12:15Erik I Put everything to SRAM. SYSCLK_FREQ_72MHz defined Scope measurements: SPI1_SCK pin (BRR configured to SPI_BaudRatePrescaler_4) ~18MHz, MCO(PLLCLK_DIV2) pin ~36 MHz. So APB2 and PLL runs at 72MHz. ISR respo...

trisf · 2011-12-01

Posted on December 02, 2011 at 08:24Hi Erik If core runs at 36MHz then 360ns is ok. MCO pin (RCC_MCO_PLLCLK_Div2) runs at 36MHz. Core clock is 72 MHz? If core runs at 72MHz isn`t it 72/12=6MHz=166ns? Thats why i was so confused.

trisf · 2011-12-01

Posted on December 01, 2011 at 14:381) Measurements done with digital channels of oscilloscope 2) STM32F10X_HD defined so I assume it is 72 MHz (8MHz(external crystal)*9(PLLMUL=0x7)) 3) thank you for pointing to pclk1, its my mistake 4) flash pre-f...

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Stm32f103 HSE external clock and PLL question

stm32f103re EXTI interrupt response time

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