STM32F103C8T6 SPI DMA wrong bytes position

[tn88test]

Posted on January 27, 2015 at 10:25

My STM32f103C8T6 works as a slave. The SPI DMA worked fine if I put the NSS pin of the slave to the ground or set the pins config to software. But if I put the NSS pin of the slave to the gpio pin of the master, the slave received bytes in wrong position. Those received bytes are correct but in wrong position.

fx Master transmits bytes 1, 2, 3, 4, 5 and slave received maybe 3, 1, 2, 4, 5. Had anyone had been dealing with this problem? And how can I reset DMA when received wrong data? Thanks! #stm32f1 #nss-spi-dma

[Tesla DeLorean]

Posted on January 28, 2015 at 02:03

I guess you'd look very carefully at the code, and review and trap the condition on a logic analyzer. If you know what the signals are doing it might be more apparent what the real issue is.

[tn88test]

Posted on January 28, 2015 at 07:55

My bad it was the cable. After replacing it with another, it's now working fine. Thank you for your help!

[tn88test]

Posted on January 29, 2015 at 08:12 Is there a way to reset DMA current transfer address in case of noise affecting SPI bus? fx When the slave misses one clock signal, the master transmits ''1, 2, 3, 4, 5'' and the slave always received ''5, 1, 2, 3, 4''. I read the datasheet and it says the current transfer register is not accessible by software. Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software.