STM32F103C8 Incorrect HCLK Issue

[ankitmcgill]

Posted on February 04, 2016 at 06:05

I am using a minimal develpment board based on STM32F103C8. The board has an external crystal of 8Mhz.

I am trying to use PLL as my clock source (with input from HSE 8Mhz) upon boot but facing the following 2 issues: 1. When I use PLL multiplier as 9, the clock does not get generated at all. 2. When I use PLL multiplier as 8, the clock does get generated. SYSCLK is 64Mhz,

however my HCLK is half of SYSCLK even though I am configuring it to be the same as SYSCLK

Below is my code (using PLL multiplier 8)

#include ''stm32f10x.h''

#include ''delay.h''


void
setupClock(
void
);

void
setupPins(
void
);


int
main(
void
)

{

RCC_ClocksTypeDef clock;


setupClock();

setupPins();


RCC_GetClocksFreq(&clock);

/*if(clock.HCLK_Frequency==64000000)

{

GPIO_SetBits(GPIOA, GPIO_Pin_6);

}*/


if
(RCC_GetSYSCLKSource() == 0x08 && clock.SYSCLK_Frequency == 64000000 && clock.HCLK_Frequency==32000000)

{

GPIO_SetBits(GPIOA, GPIO_Pin_6);

}


while
(1)

{

/*GPIO_SetBits(GPIOA, GPIO_Pin_6);

Delay_Ms(1000);

GPIO_ResetBits(GPIOA, GPIO_Pin_6);

Delay_Ms(1000);*/

}

}


void
setupClock(
void
)

{

ErrorStatus result;


RCC_DeInit();


RCC_HSEConfig(RCC_HSE_ON);

result = RCC_WaitForHSEStartUp();

if
(result==SUCCESS)

{ 

FLASH_PrefetchBufferCmd(ENABLE);

FLASH_SetLatency(FLASH_Latency_2);


//PLLCLK = (8Mhz * 9 = 72Mhz

RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_8);

RCC_PLLCmd(ENABLE);


//wait till PLL ready

while
(RCC_GetFlagStatus(RCC_FLAG_PLLRDY)==RESET)

{

}


//set PLL as SYSCLK source

RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);


//wait to verify pll is being used aS SYSCLK source

while
(RCC_GetSYSCLKSource() != 0x08)

{

}


//RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

//setupPins();

//GPIO_SetBits(GPIOA, GPIO_Pin_6);


RCC_HCLKConfig(RCC_SYSCLK_Div1);

RCC_PCLK1Config(RCC_SYSCLK_Div2);

RCC_PCLK2Config(RCC_SYSCLK_Div1);


SystemCoreClockUpdate();

}

else

{


}


//enable clock to GPIOA

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

}


void
setupPins(
void
)

{

GPIO_InitTypeDef gpio;


//set A6 as output

gpio.GPIO_Mode = GPIO_Mode_Out_PP;

gpio.GPIO_Pin = GPIO_Pin_6;

gpio.GPIO_Speed = GPIO_Speed_2MHz;

GPIO_Init(GPIOA, &gpio);

}

When I run the code, the led connected to PORT A6 lights up. Please help. This is driving me nuts. I have checked it over and over again but can't find any issues

[pkumar1883]

Posted on February 04, 2016 at 07:07

Dear Ankit,

Please verify the following point in your code-- 1. In file stm32f10x.h select right device

#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 

/* #define STM32F10X_LD */
/*!< STM32F10X_LD: STM32 Low density devices */

/* #define STM32F10X_LD_VL */
/*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */

/* #define STM32F10X_MD */
/*!< STM32F10X_MD: STM32 Medium density devices */

/* #define STM32F10X_MD_VL */
/*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */

/* #define STM32F10X_HD */
/*!< STM32F10X_HD: STM32 High density devices */

/* #define STM32F10X_HD_VL */
/*!< STM32F10X_HD_VL: STM32 High density value line devices */

/* #define STM32F10X_XL */
/*!< STM32F10X_XL: STM32 XL-density devices */

/* #define STM32F10X_CL */
/*!< STM32F10X_CL: STM32 Connectivity line devices */

#endif

2. In file system_stm32f10x.c configure system clock frequency 72MHz-

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

/* #define SYSCLK_FREQ_HSE HSE_VALUE */

#define SYSCLK_FREQ_24MHz 24000000

#else

/* #define SYSCLK_FREQ_HSE HSE_VALUE */

/* #define SYSCLK_FREQ_24MHz 24000000 */

/* #define SYSCLK_FREQ_36MHz 36000000 */

/* #define SYSCLK_FREQ_48MHz 48000000 */

/* #define SYSCLK_FREQ_56MHz 56000000 */

#define SYSCLK_FREQ_72MHz 72000000

#endif

3. Setup your clock as follows--

void
setupClock(
void
)

{

RCC_HCLKConfig(RCC_SYSCLK_Div1);

RCC_PCLK2Config(RCC_HCLK_Div1);

RCC_PCLK1Config(RCC_HCLK_Div2);

FLASH_SetLatency(FLASH_Latency_2);

FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);



RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9);

RCC_PLLCmd(ENABLE);

while
(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) {}



RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

while
(RCC_GetSYSCLKSource() != 0x08){} 

}

[ankitmcgill]

Posted on February 04, 2016 at 07:46

Hahaha I love this. One issue gets solved and another one crops up! Learning ARM is certainly fun ;p

kk, Thanks for your suggestion. You're a lifesaver. The only reason I was setting up the clocks myself was because I could not figure out why on earth my system_stm32f10x.c was not initializing the clock properly to use HSE and SYSCLK=72Mhz. After breaking my head over it for a day, I gave up and proceeded to set up clocks myself. Although the define in stm32f10x.h should not have any effect on my clock code, based on your suggestion I decided to check it again one last time. This is what I found

#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)

/* #define STM32F10X_LD */
/*!< STM32F10X_LD: STM32 Low density devices */

/* #define STM32F10X_LD_VL */
/*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */

#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */

/* #define STM32F10X_MD_VL */
/*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */

/* #define STM32F10X_HD */
/*!< STM32F10X_HD: STM32 High density devices */

/* #define STM32F10X_HD_VL */
/*!< STM32F10X_HD_VL: STM32 High density value line devices */

/* #define STM32F10X_XL */
/*!< STM32F10X_XL: STM32 XL-density devices */

/* #define STM32F10X_CL */
/*!< STM32F10X_CL: STM32 Connectivity line devices */

#endif

Notice how stupidly I had uncommented #define STM32_F10X_MD. I had removed the leading /* but not the trailing */.No wonder my clocks were messed up. Fixing this and disabling my clock initialization code, gives me the proper clock of SYSCLK=HCLK=72Mhz, Which creates a new question, What was wrong with my clock initialization code?

[Msing.4]

What about HSE_Config to enable the hse (hse_on)?​ And I am bit confused about the default state configuration of clock .is it working on internal rc oscillator 8mhz ?

Because as I have checked the default state of clock on stm studio using get_clock function it was showing 72 Mhz using pll.​

[Tesla DeLorean]

You're digging up an almost 3 year thread, let's not do that. You're arguing with ghosts.

The part starts with the 8 MHz HSI, the PLL from the HSI has a max setting of 64 MHz.

In most cases the SPL implementation should have the clocks enabled/running via the CMSIS SystemInit() function, except for a few broken tool chains. Most often this is a 72 MHz PLL running from an 8 MHz external HSE. Check board for specifics, it is not set in stone.

[Msing.4]

Oh, I have not noticed the post date . Actually I am new to the community and as I found the code for pll and I jumped with my query . I am really sorry for that .

Thanks for your answer and I am implementing cmsis and SPL for codingby using keil ide . I used stm studio for debugging purpose and the value I got 72mhz using pll I am not sure whether it is by hse or hsi.

But anyway your answer is very helpful for me for understanding purpose.​