2019-09-24 03:30 AM
We are porting a piece of software from STM32F1 to a STM32F091.
One part of the software is using bit banding. But in the library heade is no definition for the bit danding area in the memory.
I fear bit banding is not supported by this special device? Is that correct?
Solved! Go to Solution.
2019-09-24 03:32 AM
'F0 is based on Cortex-M0 core, which does not support bit-banding (the same applies to 'L0/Cortex-M0+, 'F7/'H7/Cortex-M7). You'll have to rewrite your code.
JW
2019-09-24 03:32 AM
'F0 is based on Cortex-M0 core, which does not support bit-banding (the same applies to 'L0/Cortex-M0+, 'F7/'H7/Cortex-M7). You'll have to rewrite your code.
JW
2019-09-24 03:34 AM
AFAIK, Cortex M0 devices (i.e. the core) do not support bitbanding.
I would think twice before using it anyway. Support of peripheral access depends very much on vendors, and is hardly portable.
2019-09-24 04:04 AM
Yes, portability is an issue, but that's generally an issue in the mcu world, not only for this particular feature; so one has to be aware of it and the possible pitfalls all the time anyways.
> Support of peripheral access depends very much on vendors
Can you please extend on this?
JW
2019-09-24 04:26 AM
Pretty sure Fujitsu (whatever it is called now) Cortex M devices support bitbanding in the entire peripheral area.
ST does not.
2019-09-24 05:47 AM
Thank you for your answers.
We have the code already running on F1 and F2 derivates so this problem was unexpected.
I did not expect trouble with that feature - lesson learnded ;)
Leo
2019-09-24 05:58 AM
Ah I see, thanks.
(Fujitsu->Spansion->Cypress->soon_to_be_Infineon ;) )
While talking about competition, note that bitbanding is an optional component, and not all 'M3/'M4-based mcus chose to implement it - e.g. some of the Atmel (now MCHP) ATSAMs don't.
JW