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STM32F030R8 Timer 3

markjohnson9
Associate II
Posted on October 26, 2015 at 16:44

ST Community -

An application has the current design parameters for a Cortex M0 device STM32F030R8:

CLK: 20MHz external xtal on (PF0 & PF1 RCC OSC) internal PLL to 40MHz (25ns).

Regarding Timer 3, I want to create a delay (1-399) 25ns cycle time, in response to an external rising input edge coming into PA6. What is the preferred input channel (CHx) or ETR should be used to start the counter? I would then need to output the delayed edge on which one of the output channels? To achieve this function code should load the counter ARR or CRR to the delay time?

I realize there will be a latency but can tolerate a few cycles.

Any expertise on the internal working of TIM3 to achieve this function is appreciated. 
2 REPLIES 2
Posted on October 26, 2015 at 22:36

> Regarding Timer 3, I want to create a delay (1-399) 25ns cycle time, in response to an external rising input edge coming into PA6.

>What is the preferred input channel (CHx) or ETR should be used to start the counter?

Open the datasheet, go to the ''alternate functions'' table (Tab.12). What options do you see for TIM3 on PA6?

> I would then need to output the delayed edge on which one of the output channels?

Whichever you want, except the one you already assigned as input.

> To achieve this function code should load the counter ARR or CRR to the delay time?

To bake a cake, should I use eggs or flour? :)

Apart from the fact, that there is no CRR register in timers, ARR determines the repetition rate of the timer, and you did not mention you want to repeat something periodically. What you might have had in mind was to set the delay time into CCRx corresponding to the output channel of your choice; set that channel to output compare (CCMRy.CCxS=0), set it to toggle on compare (or to change to level of your choice, or set to one of the PWM modes - all of these might result in an edge after the delay, but all of these might require some preconditions to achieve the ''idle'' level)(CCMRy.OCxM); enable (CCER.CCxE=1); leave CNT at zero and timer disabled (CR1.CEN=0), set ARR to as high as possible (0xFFFF) (any value higher than the required delay would do, but details depend on whether and when do you want to repeat the whole thing); and set the input channel (assuming it's CH1 which it is) to capture (CCMR1.CC1S=1) and enable it (CCER.CC1E=1). Unless the output mode is ''set to xxx level upon match'', you want to stop the timer after the output level changes so that another change won't occur, e.g. in an interrupt triggered by the output compare event.   Eezy breezy. I might have omitted something.

You might want to start by reading the TIM3 chapter thoroughly.

JW

markjohnson9
Associate II
Posted on October 27, 2015 at 00:21

I meant CCR, Sorry for the typo and thanks.