Posted on January 15, 2015 at 22:22Hi,
I have a question regarding open drain configuration for SPI communication in the STM32F030x Family of MCUs.
I have successfully configured the SPI interface with open drain outputs and external pull ups (for compliance with 5v logic) for communicating with multiple slaves in 8 bit mode. The transfer of data and the replies from the slaves are correct as seen in my logic analyzer and scope. However there seems to be an odd situation where when the clock line is in open drain mode, the data read in from the receive registers is erroneous (but only the last bit of data always) and this only happens in clock idle polarity high and clock phase = 1 which is required by the slaves, i.e. If the clock idle polarity is low and phase high I have no problem, but unfortunately the timing specs are not met for my second slave.
This is a very odd issue, I am just wondering, does the STM32F030x family of micro-controllers support SPI communication with open drain outputs?
#sclk #open-drain #spi #stm32f030
