STM32 use SPI implement SWD?

[YiKai]

I want to use SPI implement SWD protocol. Found this one enter link description here

Is there any advice you can provide detail?

Have a nice day

[Uwe Bonnes]

The code is nice, thank you for the example. But beside being able to run SWD at a constant clock, what do you gain: You wait busy while the transaction is running. After the transaction there is a substantial computation to decipher the data. With bitbanging, the data bits are deciphered while they come in. So I guess that why you can get a SWCLK speed during transmission with the SPI approach, the rate at which transactions can be submitted is not higher than with bit-banging.

[S.Ma · Accepted solution]

And what speed do you expect with bit banging with a low power sysclk of 48MHz?

Here we are at 12/24 MHz. If SYSCLK is pll cranked up to 96 or 144 MHz....

One more point to look at it: When we rely on SPI FIFO, other interrupts such as USB can partially kick in while waiting at less penalty.

As Debugger is a USB to SWD bridge, it wouldn't look like using SPI being a regression.

There are some new SPI IP such as the one with STM32L4R5 supposely offering a 3 wire interface (supposely avoiding to short miso and mosi outside), with this exercise, discovered its functionality was inadequate as its behaviour seems like the half duplex SPI (with slippery SCKs)

for data deciphering, it's more like using wait dead time to time slice the computation avoiding to do all at the end. Here the data is done in chunks.

In general a HW assist is desireable to reduce SW workload and critical timings.

Anyway, I guess the answer has been provided to the question. Free speech always welcome. =)

[S.Ma]

One limitation of SPI to take note: Its prescaler is a power of 2, granularity is limited

Unless using the lovely STM32L4 where most peripherals can have a menu of various clock sources...

[S.Ma]

One comment with this trial, the clock speed change is due to the reading mode, the target logic has some delay to respond and there is no clock feedback.

In the past, I was changing the clock polarity and realized it was a wrong choice. Clock slowdown is more rugged.

As a result, we can suggest for STM32 2020 wish list that If there is a future SPI with programmable reading clock latch delay, perf could go up more.

A SPI mode with DR containing the R/W bit, the bit chunk size and up to 8 bit data controlled by DMA, SWD would be nearly fully HW without delays.

Having the possibility to flush SPI FIFO would help too.

[YiKai]

Thank you, this code is really hlepful

I wil try it soon.

Have a good day

[YiKai]

I will try my Best, I used Cypress chip, it's support up to 14 MHz

Thank you, I really learned a lot, I can't wait to test it quickly

Have a good day