STM32 pwm signal and reverse of it

[GunkutA]

The MCU I use is STM32F103C8 and I need 2 PWM signals that complete each other to %100 duty cycle. ( ie: PWM1=%60 and PWM2 =%40 ). When one PWM channel is high the other one needs to be low and vice versa.

The important part is, these two PWM signals should not be high at the same time. So I thought using 2 channels in opposite PWM mode. However, duty cycles will be changing and they will not be same throughout the code so while changing the CCR values of these channels, I believe the pattern might be broken and these signals might get high at the same time, even for a short time. 

Is there a way that I can follow to maintain that comleting PWM signals without having them high at the same time and is there a precaution or a security measure to prevent making them high at the same time?

Edit:

I need to set dead time around 50 ns, with my clock period 13.8 ns I need to set TIM1_BDTR register's DTG bits to 0x04. (These are the [0-7] bits of the BDTR register). I don't want to change the bits [8-15]. But I am not sure how can I reach and change individual bits in STM32. I guess the way I used to do in PIC does not work in STM.

So I think I can change each bit one by one as this:

TIM1_BDTR= (0<<0); 
 TIM1_BDTR= (0<<1); 
TIM1_BDTR= (1<<2);

But this seems wrong. How can I set last LS 3 bits of TIM1_BDTR to 4?

[waclawek.jan]

Read the deadline subchapter in TIM chapter in RM, as berendi said above. There are timing diagrams provided. You have to set things according to the way how they work, not according to how you think they should work.

JW

[GunkutA]

Indeed, it was intended and that correct way.

[waclawek.jan]

The root issue is, that transistors tend to "close" slower than commanded, which effectively increases the duty at their output (if you look at a single transistor; in half-brigde that results in disastrous overlap between both transistors being open at the same time). So, deadtime only compensates for that increased duty; of course, if you set it to high, it will act then excessively as duty decrease.

JW