STM32 Interleaved ADC Sample Timestamping

[Stm325]

Hi, I am using STM32L476RG-Nucleo64 boards for one of my ultrasound projects. Basically, the process is:

1)Send 2MHz pulses with pwm

2) Sample 1000points with 8-bit interleaved ADC(500 each) and DMA

3) Send ADC data through SPI.

4) Wait TIM3 to trigger again for both ADC and PWM and back to 1

Everything is working fine, only problem is that I need the time label of each sample -Or somehow calculate the Δt between them- in ADC so that I can identify the Δt of some peaks positions in the data but it is troubling me because of maxed ADC speed

I made ADC interleaved, 8-bit and 2.5 cycles to work at max speed, not like a timer-triggered ADC. Therefore I cannot measure the total 1000 sampling time for dividing by 1000 (Not sure if all samplings are done with same speed tho).

I tried to measure the time using DMA callback and ADC callback using DWT but it is saying that the time is around 35ms and I know it is wrong because I can confirm with an oscilloscope that the data window I am sampling with 1000 sampling is around 60us.

You can review the stm32 main.c from here: main.c

Note: In the code I enabled ContiniousConvMode even though it is not recommended for triggered ADC but somehow my version works with continious mode enabled and stops working when it is disabled.

Also -Maybe I am misinterpreting some concepts- but my real sampling rate seems to be a lot higher than my calculations. I set 8-bit ADC interleaved with 2.5 sampling cycle and 2 cycle delay, which should give 16 cycle for 2ADC which is 10MHz sampling rate with 80MHz clock. With this setup 100 samples should take 10us, but when I compare this with an oscilloscope, 10us difference is 150 samples which is 1.5x higher than it should be.

[TDK]

I calculate 11 cycles (2.5 sample + 8.5 conversion at 8 bit) between readings on the same ADC. The secondary ADC will also convert a channel in this time, sampling delayed by 2 cycles from the master. So that's an average of 5.5 cycles per sample. Not sure how you're calculating 16 cycles here.

At 80 MHz, that's 10.3125 us per 150 samples. Seems to line up with what you're seeing.

[Stm325]

From the calculation here atthe bottom: Stm32 Interleave 

I calculated as

2.5cycle sample(Adc1) + 2.5 cycle delay + 2.5cycle sample(Adc2) + 8.5 cycle conversion(Adc2) = 16 cycle for 2 samples

Am I doing it wrong? Thanks for the answer and I hope you are right.

[TDK · Accepted solution]

There are 16 cycles between the start of ADC1 sampling and the end of ADC2 converting, but ADC1 has already  started sampling again by that time so it's not a useful measure of effective sample rate. The delay doesn't affect things here because it doesn't cause a slowdown. ADC1 is ready to sample again immediately after it's done converting.

Calculate the time between ADC1 taking a sample and then ADC1 taking the next sample. That's 2.5 + 8.5. You get two samples during that time (one from ADC1, one from ADC2).

If you increase the delay from 2 to something larger, eventually it starts to affect things. At 4 or more sample rate will slow down. (2.5 + 4 + 2.5 + 4 = 13, which is more than 11)

[Stm325]

Oh, that's right! Now I understand, thank you so much. Another thing I also mentioned in another topic is that would using HSI would be enough to assume that these cycle numbers are exact. I don't want to add HSE to my design for size purposes, but I need to be sure about the precision. I suppose HSI accuracy was 1%, which gives around 0.6875 ns potential inaccuracy between samples, which is entirely sufficient for me.

[TDK]

Using HSI instead of HSE doesn't affect the number of cycles, it's the same calculation. It will introduce some jitter in when exactly the samples are taken and how long the signal is sampled.

[Stm325]

Thank you, also sorry for the calculation problems again but I tried to calculate the ADC  t_s using the difference where ADCs conversion phases end as it is implemented here: 

This is my version's calculation:

According to this, the time difference between 2 samples should be 5 cycles? Hope not doing anything wrong this time tho

[TDK]

Shift the second ADC1 over to the right 1 cycle. It can't sample until it's done converting.