Hi, I have an FPGA connected to the STM32 (STM32F746IGT). The FPGA is set up to work as SRAM (tested and confirmed working). I’m using the STM’s Flexible Memory Controller to read from the ‘sram’. Now this works, but after 2 read cycles, the FMC stops attempting to read the ‘sram’. I have connected a logic analyzer to confirm, I was able to observe that the FMC dose not toggle any address lines or the enable pins after a few read cycles.
The FPAG is configured to have 12 address lines, 8 data lines, NEO & NE1. The ‘sram’ has no write functionality. The ‘sram’ is filled will data internally, and a ready signal gets toggled when the ‘sram’ is full, this signals the STM to read xyz data.
It almost looks as if the FMC reads the data form an address range, then assumes there is no data change, so it does not attempt to read anymore. Has anyone had experience with this? If this is in fact what the FMC is doing, is there a way to ‘reset’ the FMC?
If any one can provide any information, it would be really appreciated. I’m looking forward to a reply. I can provide more details, if needed.
