2014-07-10 07:32 AM
2014-07-11 06:55 AM
I don't use the 'F0 but reading RM0091 I'd say this is the expected behaviour of DMA in the 'F0, when MSIZE is different from PSIZE, regardless of PINC/MINC. In other words, this is the simplest possible DMA model - no FIFO and the transfers are 1:1 - padding the missing bits with 0 (or throwing away unneeded bits, depending on the ratio of sizes and transfer direction).
However, are you sure you can't access the packet memory as 8-bit? IMO the RM is not very clear in this respect. I personally would try MSIZE=PSIZE=8-bit first. If that fails, as plan B, you might perhaps try to transfer data from ADC to the ''regular'' RAM as 8-bit, and in a second step, using a timer-triggered memory-to-packet-memory 16-bit transfer... JW2014-07-11 07:42 AM
Why couldn't you use 16-bit and halve the transfer size? Aren't the bytes just packed in contiguous memory cells?
2014-07-11 08:09 AM
> Why couldn't you use 16-bit and halve the transfer size? Aren't the bytes just packed in contiguous memory cells?
Well, the RM says something about the packet memory being 16-bit wide (RM0091 rev6, Table 113 on p.844, also on p.848 ''structured as 512 half-wordsby 16 bits''). However, further reading revealed the comment on p.872, ''The packet memory should be accessed only by byte (8-bit) or half-word (16-bit) accesses.'' Ergo, IMO, MSIZE=PSIZE=8-bit should work. JW2014-07-11 09:55 AM
2014-07-11 10:13 AM
Try to DMA into the ''normal'' RAM first.
JW2014-07-12 09:18 PM
Sorry for the delay. :)
PSIZE = 8, MSIZE = 8, ADC = 8bit, Channel1 = GND, Channel2 = VDDA using SRAM (not USB PMA) (gdb) x /100hx ain0_buffer 0x200001d0 <ain0_buffer>: 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0x200001e0 <ain0_buffer+16>: 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0x200001f0 <ain0_buffer+32>: 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 0xff00 ............................. /**********************************************************************/ PSIZE = 8, MSIZE = 8, ADC = 8bit Channel1 = VDDA, Channel2 = GND using SRAM (not USB PMA) 0x200001d0 <ain0_buffer>: 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x200001e0 <ain0_buffer+16>: 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x200001f0 <ain0_buffer+32>: 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff 0x00ff ............................. /**********************************************************************/ PSIZE = 8, MSIZE = 16, ADC = 8bit Channel1 = GND, Channel2 = VDDA using SRAM (not USB PMA) 0x200001d0 <ain0_buffer>: 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x200001e0 <ain0_buffer+16>: 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x200001f0 <ain0_buffer+32>: 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x20000200 <ain0_buffer+48>: 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff ............................. /**********************************************************************/ PSIZE = 8, MSIZE = 16, ADC = 8bit Channel1 = VDDA, Channel2 = GND using SRAM (not USB PMA) (gdb) x /100hx ain0_buffer 0x200001d0 <ain0_buffer>: 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x200001e0 <ain0_buffer+16>: 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x200001f0 <ain0_buffer+32>: 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x20000200 <ain0_buffer+48>: 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 0x00ff 0x0000 ............................. (gdb) x /100wx ain0_buffer 0x200001d0 <ain0_buffer>: 0x000000ff 0x000000ff 0x000000ff 0x000000ff 0x200001e0 <ain0_buffer+16>: 0x000000ff 0x000000ff 0x000000ff 0x000000ff 0x200001f0 <ain0_buffer+32>: 0x000000ff 0x000000ff 0x000000ff 0x000000ff 0x20000200 <ain0_buffer+48>: 0x000000ff 0x000000ff 0x000000ff 0x000000ff .............................