Hello ST Team,
Board Series: stm32f072rbt6 Discovery.
Peripheral used: SPI and DMA.
SPI mode: Full duplex slave.
DMA mode: Circular
Master clock: 500khz
Byte transfer between Master and SPI slave: 63bytes
Clock polarity and phase:
Issue:
We are transferring 63bytes of data to and from master and STM32 slave.
In DMA circular mode, we observed continuous shifts in received data and circular shift in transmission frame with respect to master slave select line or which also means start of transmission frame is not in sync with the master's slave select line. We have implemented logic to make received 63bytes data frame in correct sequence by the reference of sync byte in post processing.
But to make start of transmission frame in sync with master's slave select line, we are facing difficulty. When I did some research, I found that slave select is not been considered by DMA while transmission and reception, we must make slave select line going low should in sync with DMA circular buffer index zero.
We have followed below approaches to make this work:
1.Before while(1) in main function, checking for high to low transition of slave select line to start circular DMA. In this way we thought we can make buffer index of tx and rx circular buffer in sync with slave select line in beginning itself.
2.We wrote logic to find the circular buffer index, using CNTDR register and whenever slave select line is asserted, we will wait till the circular buffer index to become zero. As soon as the index become zero, we update the transmission buffer. In this way are trying make slave select and circular buffer 0th index value are in sync. But still the shifting issue does not resolve.
3. Implemented logic to wait until the CS line goes low(Interrupt mode) then retrieve the current counter values of the DMA circular index using __HAL_DMA_GET_COUNTER() and compares with BUFFER_SIZE. This tells you how many bytes are remaining to transfer.
If either the RX or TX counter does not match with buffer size, it indicates that the DMA circular Buffer index is not at Zero, then we will Abort and Restart DMA, to make DMA circular buffer 0th index to sync with CS line.
Observations
Tx data shifting is there and also in additional to shifting, some frames have random data too.
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We overserved that when Slave select line (NSS) pin is disabled, complete 63bytes are data not been received.
The fact is SPI slave needs, slave select line for start and stop of data transfer. So, we should not disable slave select line (NSS) on SPI slave.
Now,
DMA does not consider slave select line and SPI need's slave select line (NSS), so we cannot disable slave select line (NSS) functionality, to use this pin as external interrupt.
To retain slave select line (NSS) functionality and also get interrupt on master slave select line assertion.
I have made below connections.
-------> external interrupt pin
Master slave select line (NSS)----> connected to
-------> Slave's salve select line(NSS)
And in external interrupt pin ISR call back (NSS), we are stopping DMA on rising edge of slave select line (NSS) interrupt and starting DMA transfer on falling edge of slave select line (NSS) interrupt.
But with this approach also the issue is not resolved. Now Transmission frame is filled with 0x2F.
We have tried every possible way we can, still we are not able to resolve this issue.
Please help us to resolve this issue ASAP.
