I'm checking the default configuration of an ethernet communication project based on STM32F2 microcontroller (RM0033 stm32f207 reference manual). Where the comments I'm gone to do, they could be find on section 28.6.2 (page 881, etc). I think it doesn't mind but my ethernet application is using HAL driver layer, LwIP and no RTOS.
There I'm also looking for information about peripheral registers values and their meaning. Specially those who deal with transmission and reception DMA buffers, descriptors, FIFO buffers, etc. But I don't understand some assertion it does, because the same assertion seems to has the opposite one on another part of the same document regarding the same functionality/configuration.
Example, I was on the DMA host burst access section:
"The DMA attempts to execute fixed-length burst transfers on the AHB master interface. The maximum burst length is indicated and limited by the PBL field. The receive and transmit descriptors are always accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be read."
But then says:
"When the AHB interface is configured for fixed-length burst, then it transfers data using the best combination of INCR4, INCR8, INCR16 and SINGLE transactions."
I though they first were talking about fixed-length programming on the corresponding register, not a mix of burst length sizes.
"When the AHB interface is configured for address-aligned beats, the DMA can only align the address for beats up to size 16 (for PBL > 16), because the AHB interface does not support more than INCR16."
Looking at this register description:
"These bits indicate the maximum number of beats to be transferred in one DMA transaction."
Here, I don't know if beats means number of data units or bursts of a number of data units. Where data units are: byte, half-word or word.
PBL and RDP are fields from ETH_DMABMR register (configuration register), and data sheets says:
"PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
- The maximum number of beats (PBL) possible is limited by the size of FIFO
- The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO
- Do not program out-of-range PBL values, because the system may not behave properly."
RDP is a field that is the equivalent to PBL but only applies to RX DMA transfers. Datasheet also says:
"RDP = RxDMA PBL:
- These bits indicate the maximum number of beats to be transferred in one RxDMA transaction.
- The RxDMA always attempts to burst as specified in RDP.
- Permissible values of 1, 2, 4, 8, 16, and 32. "
I'm confused for these datasheet assertions shown before:
- Permissible values of 1, 2, 4, 8, 16, and 32.
- the DMA can only align the address for beats up to size 16.. AHB interface does not support more than INCR16.
- The receive and transmit descriptors are always accessed in *the maximum possible burst size (limited by PBL) for the 16 bytes to be read
So now, and having this other found DMA information in mind (AN4031 dma controller AN - 12 and 13 pages):
My doubts are:
When talking about INCx, where should this INCx be put? What is an INCx? Is it a burst length?
What is the legal max value of burst that can be programmed and how is it chosen?
If my project is using a default configuration that has RDP options for programing the burst size and its value is set to 32: What does exactly this 32 mean regarding to the burst size? 32 bursts of what? Is it a burst of 32 data unit? beats of 32 bursts? bursts of 32 beats? burst of 32 bytes? Burst of 32 bits?
What about the max data length to be read 16 byte-sized? If this field is 32:
- 1 byte --> 32x1 byte = 32 bytes > 16 bytes,
- 2 bytes --> if 32x2 bytes > 16 bytes and
- 4 bytes --> 32x4 bytes = 128 bytes > 16 bytes.
- What about PBL/RDP value (32) and the FIFO size (2 kB)? What a relationship between these two values is?
Please if some one could briefly making a comprehensive and better explanation I will be very grateful. Should I write a PBL value less than "32"?
