SPI write data at rising and falling edge

c_dev05 · ‎2023-09-26

Hallo,

is it possible on any STM32U5 device to write only a SPI or other serial stream, that sends data on rising and falling edge?

best regards

Issamos · ‎2023-09-26

Hello @c_dev05

For SPI, you should to write the data even in rising or in a falling edge. Can you provide more details about why you want to do this, maybe our community members and experts can give you some suggestions

Best regards.

II

TDK · ‎2023-09-26

SPI cannot do DDR-style double rate, if that's what you're asking. You can use two SPIs together to achieve this result in some cases.

If you feel a post has answered your question, please click "Accept as Solution".

waclawek.jan · ‎2023-09-26

Unless the 'U5 has a vastly different SPI as compared to other STM32, as others said above, there's no DDR-style SPI.

As a workaround, you could use SPI as a slave, generating clock by a timer, one channel set to PWM and other to Toggle; feeding the former to SPI SCK externally, and using the latter as SCK to the external device.

JW

c_dev05 · ‎2023-09-26

Thank you for the ideas so far.
I want to generate a signal as it is typically sent by stereo microphones.

rising edge: bit of left channel
falling edge: bit of right channel

WP

Issamos · ‎2023-09-26

I think you can use 2 SPI interfaces. One for the bit of left channel and one for the bit of the right channel.

Best regards.

II

waclawek.jan · ‎2023-09-27

> I want to generate a signal as it is typically sent by stereo microphones.

Do you also want to output meaningful waveforms using PDM? That would get tricky in preparing the data... i.e. convert PCM to PDM and then interlace them into one stream... I don't think there's any hardware in STM32 which would help you with that, so you'd need to do that in software; and then the question is, whether computing power available is sufficient for this.

As far as the interface itself, one more workaround could also be using two appropriately synchronized SAI channels, one outputting the clock (on the data line, from 01010101 input data) and the other the data themselves. The exact timing may get tricky; the timer-and-connecting-externally method from my previous post allows also fine-tuning clock-to-data setup time.

JW

c_dev05 · ‎2023-09-27

I want to use the MDF filter, but unfortunately there is no register for writing the input data by CPU anymore, as it was at DFSDM. So I am looking for a workaround by using the SITF filters connected to SPI.

MDF filter documentation writes: For all SPI modes, the serial data is captured using the rising and the falling edge of the selected clock.