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SPI read is getting right shifted 1 bit of every byte in STM32L476ZGT6 at 20MHZ SPI CLK(SCLK)?


I am working on STM32L476ZGT6 EVAL-Board for transferring data on the SPI to one of the audio codec which is SPI slave. I am trying to read the data from codec at 20 MHz SCLK. I am seeing that the data is getting right shifed 1 bit for of every byte. I have tried with Saleae Logic analyzer to see whether slave is responding properly, the data on the MISO line is proper but when reading the data from data register master side giving right shifed data. So the data on the bus is correct but in the DR register it is getting shifed. So something is happening in the shift register.

This is what my understanding. Anyone please explain what could be the issue.

My PCLK2 is at 80 MHz and baudrate control is fpclk/4 i.e SPI clock is at 20 MHz.

I tried at 10 MHz also and both write and reads working properly but with 20 MHz write is happening properly read is getting right shifted.

The wave forms captured in saleae logic analyzer of both 10 MHz and 20 MHz reads seems to be same. Attaching the same for reference.


Too low GPIO_OSPEEDR for the SCK pin? See errata.



Hi @Community member​ 

All SPI GPIO pins including SCLK are already set to very high frequency which is 50 MHz to 80 MHz.




20MHz is a very high frequency communication. How exactly did you connect the slave device? Post photo.

Read out and post the content of SPI registers, together with the waveforms as pictures (I can't open the format you've posted, I don't have that LA).